SEARCH · Search NASA

Results for “processor”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 595 records · Page 33

All sources NASA NTRS DOE OSTI

NASA NTRS1988

Dynamically allocating sets of fine-grained processors to running computations

Researchers explore an approach to using general purpose parallel computers which involves mapping hardware resources onto computations instead of mapping computations onto hardware. Problems such as processor allocation, task scheduling and load balancing, which have traditionally proven to be challenging, change significantly under this approach and may become amenable to new attacks. Researchers describe the implementation of this approach used by the FFP Machine whose computation and communication resources are repeatedly partitioned into disjoint groups that match the needs of available tasks from moment to moment. Several consequences of this system are examined.

Middleton, David↗

NASA NTRS1988

Stochastic simulation of charged particle transport on the massively parallel processor

Computations of cosmic-ray transport based upon finite-difference methods are afflicted by instabilities, inaccuracies, and artifacts. To avoid these problems, researchers developed a Monte Carlo formulation which is closely related not only to the finite-difference formulation, but also to the underlying physics of transport phenomena. Implementations of this approach are currently running on the Massively Parallel Processor at Goddard Space Flight Center, whose enormous computing power overcomes the poor statistical accuracy that usually limits the use of stochastic methods. These simulations have progressed to a stage where they provide a useful and realistic picture of solar energetic particle propagation in interplanetary space.

Earl, James A.↗

NASA NTRS1988

Estimating water flow through a hillslope using the massively parallel processor

A new two-dimensional model of water flow in a hillslope has been implemented on the Massively Parallel Processor at the Goddard Space Flight Center. Flow in the soil both in the saturated and unsaturated zones, evaporation and overland flow are all modelled, and the rainfall rates are allowed to vary spatially. Previous models of this type had always been very limited computationally. This model takes less than a minute to model all the components of the hillslope water flow for a day. The model can now be used in sensitivity studies to specify which measurements should be taken and how accurate they should be to describe such flows for environmental studies.

Devaney, Judy E.↗

NASA NTRS1989

High speed VLSI systems for NASA's telemetry return link processor

This paper describes the architecture of the Data Interface Facility, (DIF), a key element in NASA's advanced communications systems, and its core element, the Return Link Processor (RLP). Current activities to prototype some of the primary functions of the RLP are presented. It is shown how the prototype elements can be integrated into a full-performance DIF RLP.

Hand, Sarah L.↗

NASA NTRS1991

Processor Reformats Data For Transmission In Bursts

Data-processor-and-buffer electronic system receives audio signals digitized in first standard format at relatively low data rate, rearranges data for transmission in bursts in second standard format at relatively high rate, stores second-format bursts, and releases them at higher rate upon request. Conceived for asynchronous, one-way transmission of digitized speech in outer-space communications, concept of system applied in other digital communication systems in which data transmitted from low-rate sources to high-rate sinks not synchronized with sources.

Steele, Glen F.↗

NASA NTRS1991

Improved Remapping Processor For Digital Imagery

Proposed digital image processor improved version of Programmable Remapper, which performs geometric and radiometric transformations on digital images. Features include overlapping and variably sized preimages. Overcomes some of limitations of image-warping circuit boards implementing only those geometric tranformations expressible in terms of polynomials of limited order. Also overcomes limitations of existing Programmable Remapper and made to perform transformations at video rate.

Fisher, Timothy E.↗

NASA NTRS1990

Distributed digital signal processors for multi-body structures

Several digital filter designs were investigated which may be used to process sensor data from large space structures and to design digital hardware to implement the distributed signal processing architecture. Several experimental tests articles are available at NASA Langley Research Center to evaluate these designs. A summary of some of the digital filter designs is presented, an evaluation of their characteristics relative to control design is discussed, and candidate hardware microcontroller/microcomputer components are given. Future activities include software evaluation of the digital filter designs and actual hardware inplementation of some of the signal processor algorithms on an experimental testbed at NASA Langley.

Lee, Gordon K.↗

NASA NTRS1990

Study on fault-tolerant processors for advanced launch system

Issues related to the reliability of a redundant system with large main memory are addressed. The Fault-Tolerant Processor (FTP) for the Advanced Launch System (ALS) is used as a basis for the presentation. When the system is free of latent faults, the probability of system crash due to multiple channel faults is shown to be insignificant even when voting on the outputs of computing channels is infrequent. Using channel error maskers (CEMs) is shown to improve reliability more effectively than increasing redundancy or the number of channels for applications with long mission times. Even without using a voter, most memory errors can be immediately corrected by those CEMs implemented with conventional coding techniques. In addition to their ability to enhance system reliability, CEMs (with a very low hardware overhead) can be used to dramatically reduce not only the need of memory realignment, but also the time required to realign channel memories in case, albeit rare, such a need arises. Using CEMs, two different schemes were developed to solve the memory realignment problem. In both schemes, most errors are corrected by CEMs, and the remaining errors are masked by a voter.

Shin, Kang G.↗

NASA NTRS1991

Frequency domain laser velocimeter signal processor

A new scheme for processing signals from laser velocimeter systems is described. The technique utilizes the capabilities of advanced digital electronics to yield a signal processor capable of operating in the frequency domain maximizing the information obtainable from each signal burst. This allows a sophisticated approach to signal detection and processing, with a more accurate measurement of the chirp frequency resulting in an eight-fold increase in measurable signals over the present high-speed burst counter technology. Further, the required signal-to-noise ratio is reduced by a factor of 32, allowing measurements within boundary layers of wind tunnel models. Measurement accuracy is also increased up to a factor of five.

Meyers, James F.↗

NASA NTRS1989

Data compression for Eos on-board SAR processor

A lightweight, low-power, real-time data compressor design for the Earth Observing System (Eos) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-micron CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.

Chang, C. Y.↗

NASA NTRS1990

Fault-tolerant parallel processors for avionics with reduced maintenance

Architectural issues and approaches for implementing fault-tolerant parallel processors in avionics systems and other dedicated applications requiring high levels of dependability are discussed. For these systems it is desirable to provide both a high degree of fault tolerance and a system that can operate for extended periods of time without external maintenance. With current technology it is possible to operate dependably for months between maintenance events. The longer-term goal should be maintenance-free operation (a computer that outlasts its host system). It is argued that new high-density packaging techniques may make this type of long-life fault-tolerant design an attractive choice in controlling the life-cycle costs of the next generation of systems.

Rennels, David A.↗

NASA NTRS1992

Acousto-Optical/Electronic Processor For SAR

Lightweight, compact, low-power apparatus processes synthetic-aperture-radar (SAR) returns in real time, providing imagery aboard moving aircraft or spacecraft platform. Processor includes optical and electronic subsystems that, together, resolve range and azimuth coordinates of radar targets by combination of spatial and temporal integrations.

Bicknell, T. J.↗

NASA NTRS1992

Front-End Processor For Metrology-Information System

Front-end processor for NASA Metrology Information System (NMIS) is real-time relational data-base computer system designed to distribute processing for NMIS mainframe system or run as stand-alone local-area-network data-base system. System used in large calibration laboratories for work control and to maintain records of calibration, repair, costs, manpower usage, traceability, and other pertinent facts about instruments supported by laboratories. Provides enhancements to existing NASA Metrology Information System and batches upload to minimize mainframe I/O at times of heavy usage.

Muse, Walter S.↗

NASA NTRS1992

Hypercluster Parallel Processor

Hypercluster computer system includes multiple digital processors, operation of which coordinated through specialized software. Configurable according to various parallel-computing architectures of shared-memory or distributed-memory class, including scalar computer, vector computer, reduced-instruction-set computer, and complex-instruction-set computer. Designed as flexible, relatively inexpensive system that provides single programming and operating environment within which one can investigate effects of various parallel-computing architectures and combinations on performance in solution of complicated problems like those of three-dimensional flows in turbomachines. Hypercluster software and architectural concepts are in public domain.

Blech, Richard A.↗

NASA NTRS1990

JPL's Real-Time Weather Processor project (RWP) metrics and observations at system completion

As an integral part of the overall upgraded National Airspace System (NAS), the objective of the Real-Time Weather Processor (RWP) project is to improve the quality of weather information and the timeliness of its dissemination to system users. To accomplish this, an RWP will be installed in each of the Center Weather Service Units (CWSUs), located in 21 of the 23 Air Route Traffic Control Centers (ARTCCs). The RWP System is a prototype system. It is planned that the software will be GFE and that production hardware will be acquired via industry competitive procurement. The ARTCC is a facility established to provide air traffic control service to aircraft operating on Instrument Flight Rules (IFR) flight plans within controlled airspace, principally during the en route phase of the flight. Covered here are requirement metrics, Software Problem Failure Reports (SPFRs), and Ada portability metrics and observations.

Loesh, Robert E.↗

NASA NTRS1991

Autonomous space processor for orbital debris

The development of an Autonomous Space Processor for Orbital Debris (ASPOD) was the goal. The nature of this craft, which will process, in situ, orbital debris using resources available in low Earth orbit (LEO) is explained. The serious problem of orbital debris is briefly described and the nature of the large debris population is outlined. The focus was on the development of a versatile robotic manipulator to augment an existing robotic arm, the incorporation of remote operation of the robotic arms, and the formulation of optimal (time and energy) trajectory planning algorithms for coordinated robotic arms. The mechanical design of the new arm is described in detail. The work envelope is explained showing the flexibility of the new design. Several telemetry communication systems are described which will enable the remote operation of the robotic arms. The trajectory planning algorithms are fully developed for both the time optimal and energy optimal problems. The time optimal problem is solved using phase plane techniques while the energy optimal problem is solved using dynamic programming.

Ramohalli, Kumar↗

NASA NTRS1992

Distributed digital signal processors for multi-body flexible structures

Multi-body flexible structures, such as those currently under investigation in spacecraft design, are large scale (high-order) dimensional systems. Controlling and filtering such structures is a computationally complex problem. This is particularly important when many sensors and actuators are located along the structure and need to be processed in real time. This report summarizes research activity focused on solving the signal processing (that is, information processing) issues of multi-body structures. A distributed architecture is developed in which single loop processors are employed for local filtering and control. By implementing such a philosophy with an embedded controller configuration, a supervising controller may be used to process global data and make global decisions as the local devices are processing local information. A hardware testbed, a position controller system for a servo motor, is employed to illustrate the capabilities of the embedded controller structure. Several filtering and control structures which can be modeled as rational functions can be implemented on the system developed in this research effort. Thus the results of the study provide a support tool for many Control/Structure Interaction (CSI) NASA testbeds such as the Evolutionary model and the nine-bay truss structure.

Lee, Gordon K. F.↗

NASA NTRS1991

NASA/DOD Aerospace Knowledge Diffusion Research Project. Paper 20: Engineers as information processors: A survey of US aerospace engineering faculty and students

U.S. aerospace engineering faculty and students were surveyed as part of the NASA/DoD Aerospace Knowledge Research Project. Faculty and students were viewed as information processors within a conceptual framework of information seeking behavior. Questionnaires were received from 275 faculty members and 640 students, which were used to determine: (1) use and importance of information sources; (2) use of specific print sources and electronic data bases; (3) use of information technology; and (4) the influence of instruction on the use of information sources and the products of faculty and students. Little evidence was found to support the belief that instruction in library or engineering information use has significant impact either on broadening the frequency or range of information products and sources used by U.S. aerospace engineering students.

Holland, Maurita Peterson↗