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At least 595 records · Page 33

The identification of the variation of atherosclerosis plaques by invasive and non-invasive methods

Computer-enhanced visualization of coronary arteries and lesions within them is discussed, comparing invasive and noninvasive methods. Trial design factors in computer lesions assessment are briefly discussed, and the use of the computer edge-tracking technique in that assessment is described. The results of a small pilot study conducted on serial cineangiograms of men with premature atherosclerosis are presented. A canine study to determine the feasibility of quantifying atherosclerosis from intravenous carotid angiograms is discussed. Comparative error for arterial and venous injection in the canines is determined, and the mode of processing the films to achieve better visualization is described. The application of the computer edge-tracking technique to an ultrasound image of the human carotid artery is also shown and briefly discussed.

Selzer, R. H.↗

Design and performance of the Stratospheric Aerosol and Gas Experiment II (SAGE II) instrument

Design and performance data are analyzed for the Stratospheric Aerosol and Gas Experiment II (SAGE II) instrument, which has been developed for the NASA Earth Radiation Budget Satellite (ERBS). SAGE II is designed to monitor globally, from 70 degrees S to 70 degrees N latitude, the vertical distribution of stratospheric aerosols, ozone, water vapor, and nitrogen dioxide by measuring the extinction of solar radiation through the earth's atmosphere during the ERBS observatory solar occultations. A flat scanning mirror reflects solar radiation into a Cassegrain type telescope, which forms a solar image on the entrance slit of a grating spectrometer. The instantaneous-field-of-view of the SAGE II is scanned along the vertical solar diameter by the elevation scan mirror. The optical system is contained within an azimuth gimbal which tracks the solar radiometric centroid during the data event, while the spectrometer isolates seven spectral wavelengths from 0.385-1.02 micrometers. The seven channels of the spectrometer use silicon photodiode dedectors operated in the photovoltaic mode. The detector outputs are multiplexed into a serial data stream for readout by the ERBS telemetry system, with each output being sampled 64 times per second and digitized to 12 bit resolution.

Zaun, N. H.↗

Reed-Solomon Encoder

Report presents mathematical principles of Berlekamp bit serial multiplier algorithm and its application to design of very-large-scale integrated (VLSI) encoders for Reed-Solomon error-correcting codes. Structure made readily on single chip of negatively doped channel metal oxide semiconductor.

Troung, T. K.↗

Feasibility study for a generalized gate logic software simulator

Unit-delay simulation, event driven simulation, zero-delay simulation, simulation techniques, 2-valued versus multivalued logic, network initialization, gate operations and alternate network representations, parallel versus serial mode simulation fault modelling, extension of multiprocessor systems, and simulation timing are discussed. Functional level networks, gate equivalent circuits, the prototype BDX-930 network model, fault models, identifying detected faults for BGLOSS are discussed. Preprocessor tasks, postprocessor tasks, executive tasks, and a library of bliss coded macros for GGLOSS are also discussed.

Mcgough, J. G.↗

Rodent CNS neuron development: Timing of cell birth and death

Data obtained from a staged series of single paired injections of tritiated thymidine to pregnant Wistar rats or C57B16/j mice on selected embryonic days and several postnatal times are reported. All injected specimens were allowed to come to term, each litter culled to six pups and specimens were sacrificed on PN28, with fixation and embedding for paraffin and plastic embedding. The results are derived from serial paraffin sections of PN28 animals exposed to autoradiographic processing and plotted with respect to heavily labelled cell nuclei present in the selected brain stem nuclei and sensory ganglia. Counts from each time sample/structure are totalled and the percentage of cells in the total labelled population/structure represented by each injection time interval plotted.

Keefe, J. R.↗

Algorithms for solving large sparse systems of simultaneous linear equations on vector processors

Very efficient algorithms for solving large sparse systems of simultaneous linear equations have been developed for serial processing computers. These involve a reordering of matrix rows and columns in order to obtain a near triangular pattern of nonzero elements. Then an LU factorization is developed to represent the matrix inverse in terms of a sequence of elementary Gaussian eliminations, or pivots. In this paper it is shown how these algorithms are adapted for efficient implementation on vector processors. Results obtained on the CYBER 200 Model 205 are presented for a series of large test problems which show the comparative advantages of the triangularization and vector processing algorithms.

David, R. E.↗

The vectorization of a ray tracing program for image generation

Ray tracing is a widely used method for producing realistic computer generated images. Ray tracing involves firing an imaginary ray from a view point, through a point on an image plane, into a three dimensional scene. The intersections of the ray with the objects in the scene determines what is visible at the point on the image plane. This process must be repeated many times, once for each point (commonly called a pixel) in the image plane. A typical image contains more than a million pixels making this process computationally expensive. A traditional ray tracing program processes one ray at a time. In such a serial approach, as much as ninety percent of the execution time is spent computing the intersection of a ray with the surface in the scene. With the CYBER 205, many rays can be intersected with all the bodies im the scene with a single series of vector operations. Vectorization of this intersection process results in large decreases in computation time. The CADLAB's interest in ray tracing stems from the need to produce realistic images of mechanical parts. A high quality image of a part during the design process can increase the productivity of the designer by helping him visualize the results of his work. To be useful in the design process, these images must be produced in a reasonable amount of time. This discussion will explain how the ray tracing process was vectorized and gives examples of the images obtained.

Plunkett, D. J.↗

MST radar transmitter control and monitor system

A generalized transmitter control and monitor card was developed using the Intel 8031 (8051 family) microprocessor. The design was generalized so that this card can be utilized for virtually any control application with only firmware changes. The block diagram appears in Figure 2. The card provides for local control using a 16 key keypad (up to 64 keys are supported). The local display is four digits of 7 segment LEDs. The display can indicate the status of all major system parameters and provide voltage readout for the analog signal inputs. The card can be populated with only the chips required for a given application. Fully populated, the card has two RS-232 serial ports for computer communications. It has a total of 48 TTL parallel lines that can define as either inputs or outputs in groups of four. A total of 32 analog inputs with a 0-5 volt range are supported. In addition, a real-time clock/calendar is available if required. A total of 16 k bytes of ROM and 16 k bytes of RAM is available for programming. This card can be the basis of virtually any monitor or control system with appropriate software.

Brosnahan, J. W.↗

The VAX/VMS device driver and user operation program for the Midwestern Astronomical Data Reduction and Analysis Facility PDS microdensitometer

The Midwestern astronomical data reduction and analysis facility (MADRAF) PDS microdensitometer which was the first astronomical PDS which was provided with a Motorola 6800 microprocessor control/interface and will be interfaced to a 32-bit instruction computer operating in a multiuser environment is outlined. Command and response handshaking are handled on an RS 232 serial line while data transfer occurs on a dedicated Direct Memory Access line. This set of conditions necessitated the creation of a specialized device for the system. The general outline of this software is discussed. The availability of an extraordinarily powerful computer opened the possibility of a user operating program of great versatility with diverse data destinations and formats, automatic documentation, and an extensive set of utilities which facilitate operations.

Anderson, C. M.↗

Memory-based parallel data output controller

A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.

Stattel, R. J.↗

Research in the design of high-performance reconfigurable systems

An initial design for the Bit Processor (BP) referred to in prior reports as the Processing Element or PE has been completed. Eight BP's, together with their supporting random-access memory, a 64 k x 9 ROM to perform addition, routing logic, and some additional logic, constitute the components of a single stage. An initial stage design is given. Stages may be combined to perform high-speed fixed or floating point arithmetic. Stages can be configured into a range of arithmetic modules that includes bit-serial one or two-dimensional arrays; one or two dimensional arrays fixed or floating point processors; and specialized uniprocessors, such as long-word arithmetic units. One to eight BP's represent a likely initial chip level. The Stage would then correspond to a first-level pluggable module. As both this project and VLSI CAD/CAM progress, however, it is expected that the chip level would migrate upward to the stage and, perhaps, ultimately the box level. The BP RAM, consisting of two banks, holds only operands and indices. Programs are at the box (high-level function) and system level. At the system level initial effort has been concentrated on specifying the tools needed to evaluate design alternatives.

Slotnick, D. L.↗

A versatile ground data display system for Spacelab experiments

A microprocessor-based data capture and display system suited to the needs of many Spacelab experimenters is described. Although developed specifically for the needs of the FAUST UV astronomy telescope, several features of the system may make it attractive to other groups who need to interact with their Spacelab data in real or near-real time. The display system captures data from the serial data stream originating in the Spacelab experiment computer input/output (ECIO) data channel, and can reformat and display several hundred variables per second in real time. The system offers a combination of CRT display and analog paper strip-chart output. A facility is also provided for simultaneously creating floppy-disk records of short segments of data according to prearranged criteria, to allow detailed examination of critical events in the operation of the experiment. The simplicity, economy, reliability, and flexibility of the display system suggest its use for monitoring a variety of low- and medium-data-rate Spacelab experiments.

Werthimer, D.↗

Baseband processor development for the Advanced Communications Satellite Program

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

Moat, D.↗

Photoelectric photometry of selected SAO stars. III

Photometric observations of 131 SAO stars for use in calibrating data obtained from the Near Infrared Photographic Sky Survey (NIPSS) are reported. The serial numbers of the primary NIPSS program fields in which the photometry was done are shown along with the approximate position of each field and the number of stars observed in each field. The observations are listed, showing the SAO numbers of the program stars, their 1950 equatorial coordinates, the V magnitudes, and the (V-R) and (V-I) color indices. The mean errors in magnitudes and color indices obtained by averaging deviations from the mean for each star are on the order of 0.02 mag.

Scharlach, W. W. G.↗

Dynamic-RAM Data Storage Unit

Dynamic random-access-memory (RAM) data delay and storage unit developed to insure data received from satellite is stored and not lost when satellite is not within range of ground station. Stores 256K of serial data, with independent read and write capability.

Sturman, J. C.↗

Conductive Container for Semiconductor Devices

Container for semiconductor components not only protects them against mechanical damage but ensures they are not harmed by electrostatic discharges. Container holds components in fixed positions so they can be serialized and identified from their locations. Suitable for holding components during both storing and shipping. Originally developed for microwave diodes, container concept readily adaptable to transistors and integrated circuits.

Rice, J. T.↗

Single-Chip VLSI Reed-Solomon Encoder

Reed-Solomon (RS) encoder based on Berlekamp bit-serial multiplier algorithm. RS code standard, based on code words of 255 8-bit symbols, of which 223 symbols convey information and remaining 32 are check symbols. This code enables correction of up to 16 erroneous information symbols per word. Berlekamp algorithm based on code-generating polynomial with 32 roots that occur in reciprocal pairs. Choice of algorithm permits compact design.

Truong, T. K.↗

Software used with the flux mapper at the solar parabolic dish test site

Software for data archiving and data display was developed for use on a Digital Equipment Corporation (DEC) PDP-11/34A minicomputer for use with the JPL-designed flux mapper. The flux mapper is a two-dimensional, high radiant energy scanning device designed to measure radiant flux energies expected at the focal point of solar parabolic dish concentrators. Interfacing to the DEC equipment was accomplished by standard RS-232C serial lines. The design of the software was dicated by design constraints of the flux-mapper controller. Early attemps at data acquisition from the flux-mapper controller were not without difficulty. Time and personnel limitations result in an alternative method of data recording at the test site with subsequent analysis accomplished at a data evaluation location at some later time. Software for plotting was also written to better visualize the flux patterns. Recommendations for future alternative development are discussed. A listing of the programs used in the anaysis is included in an appendix.

Miyazono, C.↗