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DOE OSTI2020

OpenACC unified programming environment for GPU and FPGA multi-hybrid acceleration

Attached accelerators have been frequently used in recent High Per- formance Computing (HPC) systems because of their high performance/power ratio. In particular, the Graphics Processing Unit (GPU) is the most popu- lar accelerator owing to its high peak FLOPS performance and high memory bandwidth supported by HBM2, etc. However, the performance of GPU depends highly on a large degree of SIMD parallelism and has difficulty sustaining a high performance on programs with frequent branch operations or a partially low degree of parallelism.By contrast, a Field Programmable Gate Array (FPGA) has received attention as a different type of accelerator than GPU as a fully reconfigurable processor fitting the target applications. The high performance of FPGA is mainly provided by a pipelined operation and optimized circuit suitable for any operation even with frequent conditional branches. We have been focusing on the flexibility of FPGA to compensate for the weakness of GPU. We believe that the coupling of GPU with FPGA can result in one of the most powerful accelerating platforms available.However, the program coding of GPU and FPGA coupling can be quite difficult for application users. Traditionally, CUDA by NVIDIA has been the most popular programming language with the largest share of GPUs used in HPC, whereas a hardware description language such as Verilog HDL has been used in FPGA programming. OpenCL coding has recently become available even on high-end FPGAs. Moreover, several recent studies have also enabled the OpenACC coding for use in FPGA. In this study, we provide a unified programming system based on OpenACC for a platform equipped with both GPU and FPGA aiming at the next-generation accelerated supercomputer framework. Our programming environment is called Multi-Hybrid OpenACC Translator (MHOAT), and in this paper, we describe the basic concept and prototype system of MHOAT based on an evaluation on the amount of coding required and the performance of a hybrid multi-device accelerated system.

Tsunashima, Ryuta↗

DOE OSTI2015

FPGA remote update for nuclear environments

The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2015

Artificial Neural Network-Based Monitoring of the Fuel Assembly Temperature Sensor and FPGA Implementation

Numerous methods have been developed around the world to model the dynamic behavior and detect a faulty operating mode of a temperature sensor. In this context, we present in this study a new method based on the dependence between the fuel assembly temperature profile on control rods positions, and the coolant flow rate in a nuclear reactor. This seems to be possible since the insertion of control rods at different axial positions and variations in flow rate of the reactor coolant results in different produced thermal power in the reactor. This is closely linked to the instant fuel rod temperature profile. In a first step, we selected parameters to be used and confirmed the adequate correlation between the chosen parameters and those to be estimated by the proposed monitoring system. In the next step, we acquired and de-noised the data of corresponding parameters, the qualified data is then used to design and train the artificial neural network. The effective data denoising was done by using the wavelet transform to remove a various kind of artifacts such as inherent noise. With the suitable choice of wavelet level and smoothing method, it was possible for us to remove all the non-required artifacts with a view to verify and analyze the considered signal. In our work, several potential mother wavelet functions (Haar, Daubechies, Bi-orthogonal, Reverse Bi-orthogonal, Discrete Meyer and Symlets) were investigated to find the most similar function with the being processed signals. To implement the proposed monitoring system for the fuel rod temperature sensor (03 wire RTD sensor), we used the Bayesian artificial neural network 'BNN' technique to model the dynamic behavior of the considered sensor, the system correlate the estimated values with the measured for the concretization of the proposed system we propose an FPGA (field programmable gate array) implementation. The monitoring system use the correlation. (authors)

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2015

Firmware development for the ATLAS TileCal sROD

TileCal is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. A main upgrade of the LHC (also called Phase-II) is planned in order to increase the instantaneous luminosity in 2022. At the TileCal level, the upgrade involves the redesign of the complete read-out architecture, affecting both the front-end and the back-end electronics. In the new read-out architecture, the front-end electronics will transmit digitized information of the full detector to the back-end system every single bunch crossing. Thus, the back-end system must provide digital calibrated information to the first level of trigger. Having all detector data per bunch crossing in the back-end will increase the precision and granularity of the trigger information, improving this way the trigger efficiencies. A reduced part of the detector, 1/256 of the total, will be equipped with the new electronics during 2014 to evaluate the proposed architecture in real conditions in the so-called 'demonstrator project'. The upgraded version of the Read-Out Driver (sROD) will be the core element of the back-end electronics in Phase-II. The sROD demonstrator is a prototype that is being developed to validate in the demonstrator project the future sROD for Phase-II. This module includes two Xilinx Series 7 Field Programmable Gate Arrays (FPGAs) for data receiving and processing and will be installed and working in an ATCA framework. A complete description of the sROD functionality in terms of firmware will be introduced. In addition, the status of the firmware development and a summary of the main milestones achieved and the future plans will be presented. (authors)

43 PARTICLE ACCELERATORS↗

DOE OSTI2015

Thomson Scattering Diagnostic Data Acquisition Systems for Modern Fusion Systems

Uniquely designed complex data acquisition system for Thomson scattering diagnostic was developed. It allows recording short duration (3-5 ns) scattered pulses with 2 GHz sampling rate and 10-bit total resolution in oscilloscope mode. The system consists up to 48 photo detector modules with 0- 200 MHz bandwidth, 1-48 simultaneously sampling ADC modules and synchronization subsystem. The photo detector modules are based on avalanche photodiodes (APD) and ultra-low noise trans-impedance amplifiers. ADC modules include fast analog to digital converters and digital units based on the FPGA (Field- Programmable Gate Array) for data processing and storage. The synchronization subsystem is used to form triggering pulses and to organize the simultaneously mode of ADC modules operation. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2023

High-bandwidth reconfigurable data acquisition card

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

Chen, Kai↗

DOE OSTI2016

Development of Criteria for Hardware Descripted Language Programmed-Devices for Safety Systems in Nuclear Power Plants in the U.S

The U.S. Nuclear Regulatory Commission (NRC) is in the process of developing a regulatory guide (RG) describing a method the staff of the NRC considers acceptable, for use in complying with NRC regulations with respect to the development of hardware description language-programmed device (HPD). Examples include: field programmable gate arrays (FPGAs), systems in the power, instrumentation, and control portions of safety systems for nuclear power plants. The regulatory framework that NRC is establishing for nuclear power plants consists of a number of regulations and supporting guidelines applicable to the development of HPD-based safety systems. The NRC issues RGs to describe to the public, methods that the NRC staff considers acceptable for use in implementing specific parts of the agency's regulations; to explain techniques that the NRC staff uses in evaluating specific problems or postulated accidents; and to provide guidance to applicants. (authors)

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2017

A qualitative assessment of current CCF guidance based on a review of safety system digital implementation changes with evolving technology - 148

This paper is a summary of a study performed in support of the US Nuclear Regulatory Commission (NRC) to evaluate current policy on software common-cause failure (CCF). The study reported in this paper is one of several that contributed to the technical basis to inform NRC staff. The study first reviewed policies and assessment guidance as discussed in the Staff Requirements Memorandum to the Secretary of the Commission, Office of the NRC (SECY) 93-087, Policy, Technical, and Licensing Issues Pertaining to Evolutionary and Advanced Light Water Reactor (ALWR) Designs, and Branch Technical Position (BTP) 7-19, Guidance on Evaluation of Defense-in-Depth and Diversity in Digital Computer-Based Instrumentation and Control Systems, as well as Chapter 7, 'Instrumentation and Controls', in NUREG-0800, Standard Review Plan for Review of Safety Analysis Reports for Nuclear Power Plants. The study then examined instrumentation and controls (I and C) technology implementations in nuclear power plants in the light of current CCF guidance. The intent was to assess whether the current position on CCF remains appropriate given the evolutions in digital safety system implementations and, if gaps in the guidance were found, to provide recommendations as to how these gaps could be closed. The methodology adopted was to review the vendors' technology and software implementation processes for digital safety systems as technology evolved. The following three representative safety systems were selected to provide illustrative examples: - Eagle 21 was selected to represent vintage microprocessor-based technology used from the 1980's to mid-1990's, - TELEPERM XS (TXS) was selected to represent second generation microprocessor-based technology used from the mid-1990's to the 2000's, and - The advanced logic system (ALS) was selected to represent the latest trend of using technology based on field programmable gate arrays (FPGAs). Technology implementations were reviewed in light of the basic premise of the NRC in BTP 7-19 (Revision 6), that software-based or software-logic-based digital system development errors are a credible source of CCF and therefore are susceptible to CCF because identical copies of the software-based logic and architecture are present in redundant divisions of safety-related systems. BTP 7-19 categorizes firmware and logic developed from software-based development systems all under software. (authors)

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2017

Secure environment establishment for FPGA-based safety-critical systems: quality management system context - 159

The paper discusses importance of secure development and operational environment establishment process, its particular stages, including security-oriented analysis and assessment of safety-critical instrumentation and control (I and C) systems. Two particular aspects are covered - security assessment and security assurance related to processes established by Quality Management System (QMS). One of the underlying ideas for the security assessment approach is in performance of gap analysis. Such analysis considers influence of all different factors within I and C system development process, and further application of Intrusion Modes and Effect Criticality Analysis (IMECA) technique. It makes the approach applicable to various safety-critical systems, considering underlying technologies (for example, Field-Programmable Gate Arrays (FPGA). Nowadays FPGA technology is often used in wide spectrum of hardware devices - from personal devices to complex I and C systems for Nuclear Power Plants (NPPs). The problem of cyber security assessment and assurance for FPGA technology in general and its application in safety-critical I and C systems in particular is not completely solved due to several reasons that cover regulations, QMS processes, implementation of development and verification activities, etc. The paper overviews existing regulations, which cover various aspects of NPP I and C systems development and operation, FPGA technology implementation, and secure development and operational environment establishment and assurance. The paper also emphasizes that complex approach should be used to identify and mitigate all specific vulnerabilities thorough the whole life cycle on the basis on Intrusion Modes, Effect and Criticality Analysis technique. The paper also proposes approach to the development of safety-critical I and C systems in the scope of cyber security assurance process at developer site. Secure development environment is described as a key factor during the development process and the paper also discusses establishment and maintenance of such environment as a part of company's Nuclear Quality Assurance's QMS. (authors)

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2017

Qualified display system architecture - 246

There is a need in the nuclear industry for a Qualified Display System (QDS) architecture as described in this paper. The function of the QDS is to process and display Regulatory Guide 1.97 post accident monitoring parameters. The QDS is implemented on the Lockheed Martin Field-Programmable Gate Array (FPGA) based Nuclear Protection and Control (NuPAC) digital platform, coupled with a Qualified Display Controller (QDC) and a Safety Display Unit (SDU). The QDS is designed to meet the requirements of IEEE 603-1991 (endorsed by Regulatory Guide 1.153, Rev. 1), IEEE 497-2002 (endorsed by Regulatory Guide 1.97, Rev. 4), and IEEE 7-4.3.2- 2003 (endorsed by Regulatory Guide 1.152, Rev. 3). The QDS is designed with flexibility such that it can be implemented in an advanced reactor design, Small Modular Reactor (SMR) with any cooling medium, or digital upgrade project for an operating nuclear plant. The QDS has four independent and redundant divisions. Each division has five layers in the architecture: Process variable input signals; Process Protection Logic (PPL); Algorithm Logic (AL), Interface Panel (IP); and Safety Display Unit (SDU). The QDS meets the following design criteria: redundancy, independence, predictability and repeatability, and diversity capability. The QDS architecture also meets the simplicity design principle. The QDS architecture design provides flexibility in the implementation in a plant. The QDS can be implemented in the design of a new advanced plant or as a digital upgrade in an operating plant. (authors)

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

DOE OSTI2017

Practical applications of model checking in the finnish nuclear industry - 281

Model checking is a powerful, formal, computer-assisted verification method that can be used to prove that a model of a (hardware or software) system fulfills stated properties. When used right, model checking can prove the correctness of instrumentation and control (I and C) system application logic, be it a software or a field-programmable gate array (FPGA) based design. The verified properties can also address unwanted functionality, making model checking a very effective method for analyzing spurious actuation. Despite the benefits, model checking is still not widely adopted in the verification of I and C systems, one exception being the Finnish nuclear industry. Since 2008, VTT has applied model checking in practical customer work related to the Olkiluoto 3 EPR, Loviisa 1 and 2 VVER-440, and Hanhikivi 1 AES-2006 nuclear power plants, on commission from either the regulator or the utilities. In this paper, we look at how the method has been used in each of these three projects. We also introduce a user-friendly, graphical modelling tool called MODCHK. We then present an overall view of the design issues detected during nine years of customer work, and one practical example. The 100% coverage means that the design errors that are found often relate to scenarios that are otherwise hard to account for (e.g., exact timing of events, or improper operator actions). (authors)

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

DOE OSTI2017

Development and application of FPGA-based logic controller - 357

The control systems of nuclear power plants contain many components which are becoming obsolete at an increasing rate. Nowadays maintenance for analog-based protection systems may be difficult as analog parts become obsolete or hard to obtain. Various studies have been conducted to address this control system hardware obsolescence issue. Those control systems of nuclear power plants have been replaced with modern digital control systems such as the programmable logic controller (PLC) and the distributed control system (DCS). The central processing unit (CPU)- based platforms such as the PLC and the DCS require an operating system (OS) and application software, and thus they might result in a common-cause failure when a problem occurs in the operating system or application software. The field programmable gate array (FPGA) is highlighted as an alternative to the conventional protection or control systems. This paper presents the development of an FPGA-based logic controller (FLC) and a diverse protection system (DPS) with the FLC platform. Protection functions for the DPS were implemented in FPGAs without any CPU or OS. (authors)

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2017

Certification of RadICS FPGA-based platform under US NRC requirements - 386

The paper discusses approach, applicable to certify digital instrumentation and control (I and C) platform under US Nuclear Regulatory Commission (NRC) requirements. Currently, Radics LLC is certifying its Field-Programmable Gate Array (FPGA)-based RadICS Platform using Platform-based test specimen. The Platform has been recently certified under IEC 61508 to meet Safety Integrity Level (SIL) 3 requirements. Up to now Radics LLC has developed a number of FPGA-based I and C applications based on RadICS Platform. Those applications include applications based on customer's specification and reverse engineering applications (Fit, Form and Function reproduction of existing equipment). The life cycles of applications include independent verification and validation of FPGA-based I and C systems/components, Commercial Grade Dedication of components for FPGA-based I and C systems, turnkey implementation of I and C project, supply of hardware, engineering tools and application design process. The paper also describes in details certification approach, which is based on Digital I and C-ISG- 06 and includes the following stages: general agreement with the US NRC, Topical Report submittal, timely responses and successful audits, and timely issuance of approved Topical Report. Such approach is supported by 10 CFR 50 Appendix B Quality Management System, which is also discussed in the paper. In addition, an overview of RadICS Platform Topical Report is presented, including its overview and structure, certification scope and obligatory appendixes. (authors)

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2023

Modbus RTU for Embedded Cyber Secure Inverter Controller

The Modbus communication protocol is a widely adopted communication standard in industrial control systems. This communication protocol is known for being reliable and straightforward to implement while being versatile in terms of its operating parameters while supporting multiple formats over various hardware infrastructures and architectures. Many intelligent devices such as Programmable Logic Controllers (PLCs), Human-Machine Interfaces (HMIs), Internet-of-Things (IoT), and various Operational Technologies (OT) utilize Modbus for their communication systems. These types of systems must communicate with each other through a standardized and central communication process. To support the integration of these modular systems, a Field-Programmable Gate Array (FPGA) can act as an embedded central routing fabric for this communication to take place. Embedded systems are versatile enough to interface with various devices and systems to accomplish various goals. Additionally, embedded systems require relatively small physical designs to minimize the required resources to facilitate the intended application by providing low-level system access. This minimization of system resources goes hand in hand with reducing the financial cost of a proposed solution or system. As remotely collaborating researchers often use FPGAs to prototype designs that are required to have a method for data transmission among systems, it is imperative to provide a baseline standard for communications among devices and systems. A typical method of implementing the Modbus RTU communication protocol in an embedded environment is using integrated logic architectures within the FPGA called “Intellectual Property (IP) cores.” IP cores can be designed using integrated logic or circuit designs to function as an embedded processor. These IP cores can then perform the required computational actions to support the Modbus RTU communication protocol by utilizing high-level programming languages such as the C programming language. The hardware description language of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allows for the control of real hardware at the logic gate and signal level. These logic gates and signals can be designed and controlled to perform desired actions based on the system design. Programming an FPGA using VHDL allows an individual to access the lowest abstraction level of the system during FPGA development. This level of abstraction is referred to as the register-transfer level (RTL), which gives access to manipulating values and variables at the register level. This register-level manipulation provides precision over creating the logical circuit within the FPGA, thus minimizing the required code to perform desired operations. The Modbus RTU communication protocol can be implemented within an FPGA using VHDL programming to establish a standardized and embedded serial communication pathway. This implementation provides a standardized communication protocol to streamline research efforts among researchers, thus increasing the efficiency of research efforts. Additionally, this Modbus RTU implementation requires fewer resources when compared to typical communication protocol implementations that utilize an IP core, reducing the hardware requirement for effective research efforts.

communication↗

DOE OSTI2023

A Real-Time ANPC Inverter Digital Twin with Integrated Design-For-Trust

The demand for renewable energy has increased over the last few years, and so has the demand for greater expectations within the energy market. This increasing trend has been accompanied by more significant usage of internet-connected devices (IoT), leading to critical electrical infrastructure being connected to the internet. Implementing internet connectivity with such devices and systems provides benefits such as improving the system's performance, facilitating irregularity and anomaly mitigation, and providing additional situational awareness for enhanced decision-making. However, enhancing the connected system with IoT introduces a drawback – a greater vulnerability to cyber-attacks. Cyber-attacks targeting critical infrastructure in the electrical sector have occurred in the United States and Ukraine. These cyber-attacks highlight and expose vulnerabilities that a system inherits when connecting to the internet. These attacks left thousands of customers without electricity for hours until operators could regain control of the electric utility grid. Therefore, to address the vulnerabilities of an internet-connected power electronic device, this work focused on the hardware layer of the system. Implementing a cyber-control system inside the hardware layer can significantly reduce the possibility of an attacker patching malicious controller firmware into a photovoltaic grid-connected inverter, thus mitigating the likelihood that the inverter becomes inactive a cyber-attack scenario. With this mitigation technique, if a cyberattack is successful and an attacker gains control of the network, a cyber-defense technique is in place to mitigate the impact of the cyber-attack. This additional protection layer was developed based on an innovative concept known as Digital Twin (DT). A DT, in this case, replicates an Active-Neutral Point Clamped (ANPC) inverter and was designed using a hardware language known as VHDL (Very High-Speed Integrated Circuit Hardware Description Language) and applied to Field-Programmable-GateArray (FPGA). The DT is embedded within the FPGA and contained in a controller board, the UCB (Unified Controller Board), developed by the University of Arkansas electrical engineering team. This UCB also contains two Digital Signal Processors (DSPs) responsible for generating associated signals to control an authentic physical inverter. These DSP signals are received and processed by the FPGA that implements the DT of an ANPC; in other words, it simulates in realtime the expected output of an actual ANPC inverter using the signals from the DSP. When a new firmware is ready to be patched, the DT provides output signals simulating behavior that a real ANPC inverter would generate with the new firmware. The new firmware is tested to check if it meets all the operational requirements established using a Design-For-Trust technique (DFTr). If the new firmware fails in at least one of the DFT tests, it is considered malicious and must be rejected. This work is divided into sections, such as Background, which explains the pieces that were used and the strategy behind this work; Process and Procedure, which explains the methodology that was adopted to prove the reliability and effectiveness of this work; Results and Discussion, where the simulations and results are described and explained; followed by Conclusion and Future work section, which concludes this work and adds possible future projects to continue this work further.

do Amaral Custodio, Paulo Vitor↗

DOE OSTI2024

Towards Automated Generation of Chiplet-Based Systems

The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based tool able to automatically generate domain-specialized systems targeting Application- Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a high-level frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frameworks), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This talk will discuss ongoing work on the SODA synthesizer to enable no-human-in-the-loop generation and design space exploration of the chiplets for highly specialized artificial intelligence accelerators. Connecting these highly specialized chiplets to general-purpose cores or programmable accelerators will allow to quickly deploy autonomous systems for scientific discovery.

Limaye, Ankur M.↗

DOE OSTI2024

A Graph Neural Network Surrogate Model for hls4ml

Recent advancements in use of machine learning (ML) techniques on field-programmable gate arrays (FPGAs) have allowed for the implementation of embedded neural networks with extremely low latency. This is invaluable for particle detectors at the Large Hadron Collider, where latency and used area are strictly bounded. The hls4ml framework is a procedure that converts trained ML model software to a synthesis result to can be used on an FPGA. However, running the pipeline is a time-consuming procedure, and there is a strong risk of failure. In particular, it may not be possible to successfully convert a model into a synthesis result, or the resource consumption of the model may exceed the resources of the target FPGA. To aid with this development, we introduce wa-hls4ml, a surrogate model using a graph neural network to emulate the structure of the source models. The goal is to estimate the chance of success and resource consumption of a given model when passed through the hls4ml pipeline, without needing to run the pipeline.

Plotnikov, Dennis↗

DOE OSTI2024

Calibration of the analog beam-signal hardware for the credited engineered beam power limit system at the Proton Power Upgrade Project at the Spallation Neutron Source

A programmable signal processor-based credited safety control that calculates pulsed beam power based on beam kinetic energy and charge was designed as part of the Proton Power Upgrade (PPU) project at the Spallation Neutron Source (SNS). The system must reliably shut off the beam if the average power exceeds 2.145 MW averaging over 60 seconds. System calibration requires pedigree in measurements, calibration setup, and calculations. This paper discusses the calibration of the analog beam signal components up to and including the Analog Digital Convertors (ADCs) for implementation into the Safety Programmable Logic Controllers (PLCs) and Field Programmable Gate Arrays (FPGAs).

Bobrek, Miljko↗