Search NASA⌕ Search

SEARCH · Search NASA

Results for “PROCESSORS”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 613 records · Page 34
All sourcesNASA NTRSDOE OSTI
NASA NTRS1975

Feasibility study for the implementation of NASTRAN on the ILLIAC 4 parallel processor

The ILLIAC IV, a fourth generation multiprocessor using parallel processing hardware concepts, is operational at Moffett Field, California. Its capability to excel at matrix manipulation, makes the ILLIAC well suited for performing structural analyses using the finite element displacement method. The feasibility of modifying the NASTRAN (NASA structural analysis) computer program to make effective use of the ILLIAC IV was investigated. The characteristics are summarized of the ILLIAC and the ARPANET, a telecommunications network which spans the continent making the ILLIAC accessible to nearly all major industrial centers in the United States. Two distinct approaches are studied: retaining NASTRAN as it now operates on many of the host computers of the ARPANET to process the input and output while using the ILLIAC only for the major computational tasks, and installing NASTRAN to operate entirely in the ILLIAC environment. Though both alternatives offer similar and significant increases in computational speed over modern third generation processors, the full installation of NASTRAN on the ILLIAC is recommended. Specifications are presented for performing that task with manpower estimates and schedules to correspond.

Field, E. I.↗
NASA NTRS1977

Microprogramed telemetry processor

Minimum hardware, reliable processor responds rapidly to changing requirements simply by changes in contents of programmable read-only memory. General purpose controller can transfer data onto and off of data bus, perform logic and arithmetic manipulations, and store pertinent data in small internal random-access memory.

Gordon, L. H.↗
NASA NTRS1976

A proposed microcomputer implementation of an Omega navigation processor

A microprocessor navigation systems using the Omega process is discussed. Several methods for correcting incoming sky waves are presented along with the hardware design which depends on a microcomputer. The control program is discussed, and block diagrams of the Omega processor and interface systems are presented.

Abel, J. D.↗
NASA NTRS1977

Multispectral image processor

Correlation clustering of 250,000 pixels are numerically classified in real time according to various image elements. Processor operates upon data supplied by Earth Resources Technology Satellite. Algorithmic signal manipulation is used to provide discrete control of individual image parameters.

Haskell, R. E.↗
NASA NTRS1976

A synthetic aperture processor using CCD signal processing techniques

Synthetic aperture radar (SAR) imaging was the most suitable technique for achieving high resolution imagery through atmospheric cloud cover. This feature was important for planetary as well as earth orbiting satellite systems, and for military aircraft applications. Such applications require onboard data processing or wide-band data transmission systems in order to handle the large amounts of raw data produced by such systems. A number of techniques were utilized in implementing SAR processors. Frequency filtering and Fourier transform operations using both optical and digital techniques were utilized in SAR processing.

Bailey, W. H.↗
NASA NTRS1976

Analytical and experimental design and analysis of an optimal processor for image registration

The author has identified the following significant results. A quantitative measure of the registration processor accuracy in terms of the variance of the registration error was derived. With the appropriate assumptions, the variance was shown to be inversely proportional to the square of the effective bandwidth times the signal to noise ratio. The final expressions were presented to emphasize both the form and simplicity of their representation. In the situation where relative spatial distortions exist between images to be registered, expressions were derived for estimating the loss in output signal to noise ratio due to these spatial distortions. These results are in terms of a reduction factor.

Mcgillem, C. D.↗
NASA NTRS1977

Development and performance of power processor system for 2-gigahertz, 200-watt amplifier for communications technology satellite

The electrical and environmental requirements for a power processor system (PPS) designed to supply the appropriate voltages and currents to a 200-watt traveling wave tube (TWT) for a communication technology satellite is described. A block diagram of the PPS, the interface requirements between the PPS and spacecraft, the interface requirements between the PPS and 200-watt TWT, and the environmental requirements of the PPS are presented. Also included are discussions of protection circuits, interlocking sequences, and transient requirements. Predictions of the flight performance, based on ground test data, are provided.

Siegert, C. E.↗
NASA NTRS1976

Development of a 30-cm ion thruster thermal-vacuum power processor

The 30-cm Hg electron-bombardment ion thruster presently under development has reached engineering model status and is generally accepted as the prime propulsion thruster module to be used on the earliest solar electric propulsion missions. This paper presents the results of a related program to develop a transistorized 3-kW Thermal-Vacuum Breadboard (TVBB) Power Processor for this thruster. Emphasized in the paper are the implemented electrical and mechanical designs as well as the resultant system performance achieved over a range of test conditions. In addition, design modifications affording improved performance are identified and discussed.

Herron, B. G.↗
NASA NTRS1977

Photon counting processor for laser velocimetry

In some of the more difficult applications of laser Doppler velocimetry such as in combustion research, transonic flow, transverse wind, and others, the optical signals are too small for classical detection methods. This paper summarizes the theory, experimental prototype hardware, and test results for a new type of high-speed photon-correlation signal processor which is being developed for weak laser velocimeter signals and other photon-resolved signals. The new system may also be considered to be a statistical digital frequency discriminator. It uses full multiplication with 10-nsec delay time and has the potential for extension to the measurement of the velocity correlations and spectra.

Mayo, W. T., Jr.↗
NASA NTRS1977

Radar speckle reduction in synthetic aperture radar processors by a moving diffuser

Some theoretical and experimental results are presented demonstrating the reduction of synthetic aperture radar speckle when a moving diffuser is placed in the processor image plane and is reimaged with a lens whose resolution is not better than the radar resolution. The resolution of the resulting radar image is determined by the resolution of this output lens.

Jain, A.↗
NASA NTRS1978

The 30-cm ion thruster power processor

A power processor unit for powering and controlling the 30 cm Mercury Electron-Bombardment Ion Thruster was designed, fabricated, and tested. The unit uses a unique and highly efficient transistor bridge inverter power stage in its implementation. The system operated from a 200 to 400 V dc input power bus, provides 12 independently controllable and closely regulated dc power outputs, and has an overall power conditioning capacity of 3.5 kW. Protective circuitry was incorporated as an integral part of the design to assure failure-free operation during transient and steady-state load faults. The implemented unit demonstrated an electrical efficiency between 91.5 and 91.9 at its nominal rated load over the 200 to 400 V dc input bus range.

Herron, B. G.↗
NASA NTRS1978

Custom large scale integrated circuits for spaceborne SAR processors

The application of modern LSI technology to the development of a time-domain azimuth correlator for SAR processing is discussed. General design requirements for azimuth correlators for missions such as SEASAT-A, Venus orbital imaging radar (VOIR), and shuttle imaging radar (SIR) are summarized. Several azimuth correlator architectures that are suitable for implementation using custom LSI devices are described. Technical factors pertaining to selection of appropriate LSI technologies are discussed, and the maturity of alternative technologies for spacecraft applications are reported in the context of expected space mission launch dates. The preliminary design of a custom LSI time-domain azimuth correlator device (ACD) being developed for use in future SAR processors is detailed.

Tyree, V. C.↗
NASA NTRS1978

On-board landmark navigation and attitude reference parallel processor system

An approach to autonomous navigation and attitude reference for earth observing spacecraft is described along with the landmark identification technique based on a sequential similarity detection algorithm (SSDA). Laboratory experiments undertaken to determine if better than one pixel accuracy in registration can be achieved consistent with onboard processor timing and capacity constraints are included. The SSDA is implemented using a multi-microprocessor system including synchronization logic and chip library. The data is processed in parallel stages, effectively reducing the time to match the small known image within a larger image as seen by the onboard image system. Shared memory is incorporated in the system to help communicate intermediate results among microprocessors. The functions include finding mean values and summation of absolute differences over the image search area. The hardware is a low power, compact unit suitable to onboard application with the flexibility to provide for different parameters depending upon the environment.

Gilbert, L. E.↗
NASA NTRS1978

Formulation of consumables management models. Volume 2: Mission planning processor user guide

A user guide for the MPP (Mission Planning Processor) is presented. The MPP is used in the evaluation of particular missions, with appropriate display and storage of related consumables data. Design goals are accomplished by the use of an on-line/demand mode computer terminal Cathode Ray Tube Display. The process is such that the user merely adds specific mission/flight functions to a skeleton flight and/or alters the skeleton. The skeleton flight includes operational aspects from prelaunch through ground support equipment connect after rollout as required to place the STS (Space Transportation System) in a parking orbit, maintain the spacecraft and crew for the stated on-orbit period and return.

Daly, J. K.↗
NASA NTRS1978

GASP-PL/I Simulation of Integrated Avionic System Processor Architectures

A development study sponsored by NASA was completed in July 1977 which proposed a complete integration of all aircraft instrumentation into a single modular system. Instead of using the current single-function aircraft instruments, computers compiled and displayed inflight information for the pilot. A processor architecture called the Team Architecture was proposed. This is a hardware/software approach to high-reliability computer systems. A follow-up study of the proposed Team Architecture is reported. GASP-PL/1 simulation models are used to evaluate the operating characteristics of the Team Architecture. The problem, model development, simulation programs and results at length are presented. Also included are program input formats, outputs and listings.

Brent, G. A.↗