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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 631 records · Page 35
All sourcesNASA NTRSDOE OSTI
NASA NTRS2015

Human Research Program Advanced Exercise Concepts (AEC) Overview

Exercise countermeasures provide benefits that are crucial for successful human spaceflight, to mitigate the spaceflight physiological deconditioning which occurs during exposure to microgravity. The NASA Human Research Program (HRP) within the Human Exploration and Operations Mission Directorate (HEOMD) is managing next generation Advanced Exercise Concepts (AEC) requirements development and candidate technology maturation to Technology Readiness Level (TRL) 7 (ground prototyping and flight demonstration) for all exploration mission profiles from Multi Purpose Crew Vehicle (MPCV) Exploration Missions (up to 21 day duration) to Mars Transit (up to 1000 day duration) missions. These validated and optimized exercise countermeasures systems will be provided to the ISS Program and MPCV Program for subsequent flight development and operations. The International Space Station (ISS) currently has three major pieces of operational exercise countermeasures hardware: the Advanced Resistive Exercise Device (ARED), the second-generation (T2) treadmill, and the cycle ergometer with vibration isolation system (CEVIS). This suite of exercise countermeasures hardware serves as a benchmark and is a vast improvement over previous generations of countermeasures hardware, providing both aerobic and resistive exercise for the crew. However, vehicle and resource constraints for future exploration missions beyond low Earth orbit will require that the exercise countermeasures hardware mass, volume, and power be minimized, while preserving the current ISS capabilities or even enhancing these exercise capabilities directed at mission specific physiological functional performance and medical standards requirements. Further, mission-specific considerations such as preservation of sensorimotor function, autonomous and adaptable operation, integration with medical data systems, rehabilitation, and in-flight monitoring and feedback are being developed for integration with the exercise countermeasures systems. Numerous technologies have been considered and evaluated against HRP-approved functional device requirements for these extreme mission profiles, and include wearable sensors, exoskeletons, flywheel, pneumatic, and closed-loop microprocessor controlled motor driven systems. Each technology has unique advantages and disadvantages. The Advanced Exercise Concepts project oversees development of candidate next generation exercise countermeasures hardware, performs trade studies of current and state of the art exercise technologies, manages and supports candidate systems physiological evaluations with human test subjects on the ground, in flight analogs and flight. The near term goal is evaluation of candidate systems in flight, culminating in an integrated candidate next generation exercise countermeasures suite on the ISS which coalesces research findings from HRP disciplines in the areas of exercise performance for muscle, bone, cardiovascular, sensorimotor, behavioral health, and nutrition for optimal benefit to the crew.

Countermeasures↗
NASA NTRS1976

Signal design study for shuttle/TDRSS Ku-band uplink

The adequacy of the signal design approach chosen for the TDRSS/orbiter uplink was evaluated. Critical functions and/or components associated with the baseline design were identified, and design alternatives were developed for those areas considered high risk. A detailed set of RF and signal processing performance specifications for the orbiter hardware associated with the TDRSS/orbiter Ku band uplink was analyzed. Performances of a detailed design of the PN despreader, the PSK carrier synchronization loop, and the symbol synchronizer are identified. The performance of the downlink signal by means of computer simulation to obtain a realistic determination of bit error rate degradations was studied. The three channel PM downlink signal was detailed by means of analysis and computer simulation.

Source record↗
NASA NTRS1985

Free-piston Stirling engine/linear alternator 1000-hour endurance test

The Free Piston Stirling Engine (FPSE) has the potential to be a long lived, highly reliable, power conversion device attractive for many product applications such as space, residential or remote site power. The purpose of endurance testing the FPSE was to demonstrate its potential for long life. The endurance program was directed at obtaining 1000 operational hours under various test conditions: low power, full stroke, duty cycle and stop/start. Critical performance parameters were measured to note any change and/or trend. Inspections were conducted to measure and compare critical seal/bearing clearances. The engine performed well throughout the program, completing more than 1100 hours. Hardware inspection, including the critical clearances, showed no significant change in hardware or clearance dimensions. The performance parameters did not exhibit any increasing or decreasing trends. The test program confirms the potential for long life FPSE applications.

Rauch, J.↗
NASA NTRS1989

Chemical calculations on Cray computers

The influence of recent developments in supercomputing on computational chemistry is discussed with particular reference to Cray computers and their pipelined vector/limited parallel architectures. After reviewing Cray hardware and software the performance of different elementary program structures are examined, and effective methods for improving program performance are outlined. The computational strategies appropriate for obtaining optimum performance in applications to quantum chemistry and dynamics are discussed. Finally, some discussion is given of new developments and future hardware and software improvements.

Taylor, Peter R.↗
NASA NTRS1989

Chemical calculations on Cray computers

The influence of recent developments in supercomputing on computational chemistry is discussed with particular reference to Cray computers and their pipelined vector/limited parallel architectures. After reviewing Cray hardware and software the performance of different elementary program structures are examined, and effective methods for improving program performance are outlined. The computational strategies appropriate for obtaining optimum performance in applications to quantum chemistry and dynamics are discussed. Finally, some discussion is given of new developments and future hardware and software improvements.

Taylor, Peter R.↗
NASA NTRS2000

A Low Cost, Self-Acting, Liquid Hydrogen Boil-Off Recovery System

PROJECT SUMMARY. 1 PROJECT OBJECTIVES. Detail Design. Final Analysis. Hardware Procurement. Component Tests. System Tests..Prototype Tests. 2. WORK PERFORMED. Detail Design. Final Analysis. Hardware Procurement. Component Tests. System Tests. Prototype Tests. 3. Results obtained. Detail Design. Final Analysis. Hardware Procurement. Component Tests. System Tests. Prototype Tests. 5. TECHNICAL MERIT AND FEASIBILITY ASSESSMENT. 6. APPENDIX A: SIZE DETAIL DRAWINGS. 7. APPENDIX B: CONSULTANTS SENSITIVITY STUDY. 8. APPENDIX C: CONSULTANTS REPORT. ROTORDYNAMIC ANALYSIS 9. SF298 REPORT DOCUMENTATION PAGE.

Pelfrey, Joy w.↗
DOE OSTI2022

Development and performance of a HemeLB GPU code for human-scale blood flow simulation

In recent years, it has become increasingly common for high performance computers (HPC) to possess some level of heterogeneous architecture - typically in the form of GPU accelerators. In some machines these are isolated within a dedicated partition, whilst in others they are integral to all compute nodes - often with multiple GPUs per node - and provide the majority of a machine's compute performance. In light of this trend, it is becoming essential that codes deployed on HPC are updated to execute on accelerator hardware. Here, in this paper, we introduce a GPU implementation of the 3D blood flow simulation code HemeLB that has been developed using CUDA C++. We demonstrate how taking advantage of NVIDIA GPU hardware can achieve significant performance improvements compared to the equivalent CPU only code on which it has been built whilst retaining the excellent strong scaling characteristics that have been repeatedly demonstrated by the CPU version. With HPC positioned on the brink of the exascale era, we use HemeLB as a motivation to provide a discussion on some of the challenges that many users will face when deploying their own applications on upcoming exascale machines.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2024

FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition

In recent years, security monitoring of public places and critical infrastructure has heavily relied on the widespread use of cameras, raising concerns about personal privacy violations. To balance the need for effective security monitoring with the protection of personal privacy, we explore the potential of optical fiber sensors for this application. This article proposes FiberFlex, an intelligent and distributed fiber sensor system. Ultizing Field Programmable Gate Arrays (FPGA) high-level synthesis (HLS) acceleration, FiberFlex offers real-time pedestrian detection by co-designing the entire pipeline of optical signal acquisition, processing, and recognition networks based on the principles of optical fiber sensing. As a promising alternative to traditional camera-based monitoring systems, FiberFlex achieves pedestrian detection by analyzing the vibration patterns caused by pedestrian footsteps, enabling security monitoring while preserving individual privacy. FiberFlex comprises three modules: First , fiber-optic sensing system: A fiber-optic distributed acoustic sensing (DAS) system is built and used to measure the ground vibration waves generated by people walking. Second , algorithms: We first collect the training data by measuring the ground vibration waves, label the data, and use the data to train the neural network models to perform pedestrian recognition. Third , hardware accelerators: We use HLS tools to design hardware modules on FPGA for data collection and pre-processing and integrate them with the downstream neural network accelerators to perform in-line real-time pedestrian detection. The final detection results are sent back from FPGA to the host CPU. We implement our system FiberFlex with the in-house built DAS system and AMD/Xilinx Kintex7 FPGA KC705 board and verify the whole system using the real-world collected data. We conduct recognition tests on five test subjects of varying ages, heights, and weights in a fixed sensing area. Each subject experienced 20 real-time recognition tests using their daily walking habits, and the subjects were given adequate rest between tests. After 100 tests on five test subjects, the overall real-time recognition accuracy exceeded \(88.0\%\) . The whole system uses 55 W of power, 33 W in the optical DAS system and 22 W in the FPGA. Relying on its end-to-end interdisciplinary design, FiberFlex seamlessly combines fiber-optic sensors with FPGA accelerators to enable low-power real-time security monitoring without compromising privacy, making it a valuable addition to the existing security monitoring network. According to FiberFlex, more valuable research can be conducted in the future, such as fall monitoring for the elderly, migration of identification networks between different application scenarios, and improvement of anti-interference performance in more complex environments. In future perception networks, where the “eyes” are not feasible, let’s use fiber optic touch instead.

Distributed↗
DOE OSTI2026

Trilinos: Enabling Scientific Computing across Diverse Hardware Architectures at Scale

Trilinos is a community-developed, open-source software framework that facilitates building large-scale, complex, multiscale, multiphysics simulation code bases for scientific and engineering problems. Since the Trilinos framework has undergone substantial changes to support new applications and new hardware architectures, this document is an update to “An Overview of the Trilinos project” by Heroux et al. (ACM Transactions on Mathematical Software, 31(3):397–423, 2005). It describes the design of Trilinos, introduces its new organization in product areas, and highlights established and new features available in Trilinos. Particular focus is put on the modernized software stack based on the Kokkos ecosystem to deliver performance portability across heterogeneous hardware architectures. This article also outlines the organization of the Trilinos community and the contribution model to help onboard interested users and contributors.

Heterogeneous Hardware Architectures↗
DOE OSTI2020

Component and Circuit Performance Measurements for Coherent Radar - A Systems Perspective

A useful performance metric for Intelligence, Surveillance, and Reconnaissance (ISR) radar systems is the Impulse Response (IPR). This is true for a fidelity metric for the signal channel, as well as a stability measure across multiple pulses. The IPR represents performance with respect to both amplitude and phase modulations of the transfer function for components, circuits, subassemblies, and even the looped radar hardware. The proper IPR performance specification limits will depend on radar operating mode. Generally, it will be the intersection of the strictest requirements.

42 ENGINEERING↗
NASA NTRS1986

Independent Orbiter Assessment (IOA): Analysis of the electrical power distribution and control/electrical power generation subsystem

The results of the Independent Orbiter Assessment (IOA) of the Failure Modes and Effects Analysis (FMEA) and Critical Items List (CIL) are presented. The IOA approach features a top-down analysis of the hardware to determine failure modes, criticality, and potential critical items. To preserve independence, this analysis was accomplished without reliance upon the results contained within the NASA FMEA/CIL documentation. This report documents the independent analysis results corresponding to the Orbiter Electrical Power Distribution and Control (EPD and C)/Electrical Power Generation (EPG) hardware. The EPD and C/EPG hardware is required for performing critical functions of cryogenic reactant storage, electrical power generation and product water distribution in the Orbiter. Specifically, the EPD and C/EPG hardware consists of the following components: Power Section Assembly (PSA); Reactant Control Subsystem (RCS); Thermal Control Subsystem (TCS); Water Removal Subsystem (WRS); and Power Reactant Storage and Distribution System (PRSDS). The IOA analysis process utilized available EPD and C/EPG hardware drawings and schematics for defining hardware assemblies, components, and hardware items. Each level of hardware was evaluated and analyzed for possible failure modes and effects. Criticality was assigned based upon the severity of the effect for each failure mode.

Patton, Jeff A.↗
NASA NTRSDate not supplied

An Overview of NASA-STD-1008: Classifications and Requirements for Testing Systems and Hardware to be Exposed to Dust in Planetary Environments

As we return to the Moon with Artemis, hardware will inevitably be exposed to lunar dust. Encountering the surface of a dusty planetary body brings significant hazards to the hardware. A team of subject matter experts across NASA were brought together to create a standard for addressing the best means of performing ground testing of hardware and systems to guard against the expected negative effects that dust may bring. This effort resulted in NASA-STD-1008: Classifications and Requirements for Testing Systems and Hardware to be Exposed to Dust in Planetary Environments. The NASA Technical Standard went through an Agency wide review and was approved for public release in September 2021.

lunar dust↗
DOE OSTI2025

Quantum Approximate Optimization Algorithm on Different Qubit Systems

Solving optimization problems is critical across many research domains, but the high dimensionality of parameter spaces often poses significant challenges. The Quantum Approximate Optimization Algorithm (QAOA) has emerged as a promising approach for accelerating optimization in the Noisy Intermediate-Scale Quantum (NISQ) era by leveraging both classical and quantum computational resources. However, its performance can vary depending on the underlying quantum hardware architecture. In this work, we evaluate the performance of QAOA on different quantum hardware platforms, specifically, superconducting transmon qubits and trapped-ion qubits, targetting real-world optimization problems formulated as fully connected Quadratic Unconstrained Binary Optimization (QUBO) instances. We evaluate both the solution quality and time-to-solution using dense QUBO matrices. Furthermore, we show that large-scale problems, such as a 100-bit QUBO instance, can be effectively tackled by integrating quantum computing with high-performance computing (HPC) resources. This study provides practical insights into the strengths and limitations of different qubit technologies and advances the application of quantum computing in solving real-world optimization problems.

Kim, Seongmin [ORNL] (ORCID:0000000159063004)↗
DOE OSTI2019

Checkpointing Strategies for Shared High-Performance Computing Platforms

Input/output (I/O) from various sources often contend for scarcely available bandwidth. For example, checkpoint/restart (CR) protocols can help to ensure application progress in failure-prone environments. However, CR I/O alongside an application's normal, requisite I/O can increase I/O contention and might negatively impact performance. In this work, we consider different aspects (system-level scheduling policies and hardware) that optimize the overall performance of concurrently executing CR-based applications that share I/O resources. We provide a theoretical model and derive a set of necessary constraints to minimize the global waste on a given platform. Our results demonstrate that Young/Daly's optimal checkpoint interval, despite providing a sensible metric for a single, undisturbed application, is not sufficient to optimally address resource contention at scale. We show that by combining optimal checkpointing periods with contention-aware system-level I/O scheduling strategies, we can significantly improve overall application performance and maximize the platform throughput. Finally, we evaluate how specialized hardware, namely burst buffers, may help to mitigate the I/O contention problem. Altogether, these results provide critical analysis and direct guidance on how to design efficient, CR ready, large -scale platforms without a large investment in the I/O subsystem.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1981

Solar Power Satellite antenna phase control system hardware simulation, phase 4. Volume 2: Analytical simulation of SPS system performance

The pilot signal parameter optimization and power transponder analyses are presented. The SPS antenna phase control system is modeled and the hardware simulation study described. Ionospheric and system phase error effects and the effects of high power amplifier phase and amplitude jitters are considered. Parameter optimization of the spread spectrum receiver, consisting of the carrier tracking loop and the code tracking loop, is described.

Lindsey, W. C.↗
NASA NTRSDate not supplied

X-57 Traction Power and Command Systems Development

This paper describes the final, as-built design of the X‑57 Maxwell aircraft power and command system architecture that implements the electrified propulsion capability. The development of the traction power, command, and avionics power subsystems proceeded as planned at the initial project critical design review, but improvements to the design were identified following the development of detailed operations concepts and integrated subsystem and system testing. The redundant architecture with A‑side and B‑side buses provided a robust framework for a developmental system that would turn out to have a lower technology readiness than had been assumed upon project formulation. As the project team identified reliability or performance gaps in the electrified propulsion powertrain components and their interactions with the other vehicle systems, the traction power, command, and avionics architectures were modified to accommodate the modified systems. Following the publication of the planned design approach at the critical design review milestone [1], the project team developed the flight hardware and software, integrated the systems, and adjusted the design and qualification activities to address gaps in the components, system architecture, and requirements as the gaps were realized. In addition to inherent challenges in development of these subsystems, the integration of this new technology with adjacent critical systems in an aircraft configuration posed additional challenges that drove design considerations across the subsystem development and the other vehicle systems. Integration complications included electromagnetic compatibility, thermal performance, and tolerance of single-point failures internal and external to the powerplant. Development of a qualification program was required for the new motors, inverters, and batteries, and hardware performance during component qualification fed back into the development process and led lessons learned and redesign of key elements.

distributed propulsion↗
NASA NTRS1979

Shuttle payload S-band communications study

The work to identify, evaluate, and make recommendations concerning the functions and interfaces of those orbiter avionic subsystems which are dedicated to, or play some part in, handling communication signals (telemetry and command) to/from payloads (spacecraft) that will be carried into orbit by the shuttle is reported. Some principal directions of the research are: (1) analysis of the ability of the various avionic equipment to interface with and appropriately process payload signals; (2) development of criteria which will foster equipment compatibility with diverse types of payloads and signals; (3) study of operational procedures, especially those affecting signal acquisition; (4) trade-off analysis for end-to-end data link performance optimization; (5) identification of possible hardware design weakness which might degrade signal processing performance.

Springett, J. C.↗