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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 649 records · Page 36
All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

Accelerated Architectures Create Programming Opportunities

In the early 2000s, industry switched to multicore microprocessors to address semiconductors' speed and power limits. However, the change was unsuccessful, leading to dire claims that “Moore's law is ending.” In conclusion, this column suggests that while the approach was sound, it needed a deeper architectural transformation. Industry has since discovered a suitable architecture, but work remains on software to support it.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Bridging Python to Silicon: The SODA Toolchain

Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements. However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages. Agile hardware design tools based on compiler techniques can help by quickly producing an application-specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description. Here, we present the software-defined accelerator (SODA) synthesizer, a modular and open-source hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multilevel representations to progressively lower and optimize the input code. Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 giga floating point operations per second (GFLOPS)/W efficiency (32-bit precision) on typical convolutional neural network operators.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

A Quench Detection and Monitoring System for Superconducting Magnets at Fermilab

A quench detection system was developed for protecting and monitoring the superconducting solenoids for the Muon-to-Electron Conversion Experiment (Mu2e) at Fermilab. The quench system was designed for a high level of dependability and long-term continuous operation. It is based on three tiers: Tier-I, FPGA-based Digital Quench Detection (DQD); Tier-II, Analog Quench Detection (AQD); and Tier-3, the quench controls and data management system. The Tier-I and Tier-II are completely independent and fully redundant systems. The Tier-3 system is based on National Instruments (NI) C-RIO and provides the user interface for quench controls and data management. It is independent from Tiers I & II. The DQD provides both quench detection and quench characterization (monitoring) capability. Both DQD and AQD have built-in high voltage isolation and user programmable gains and attenuations. The DQD and AQD also includes user configured current dependent thresholding and validation times. A 1 st article of the three-tier system was fully implemented on the new Fermilab magnet test stand for the HL-LHC Accelerator Up-grade Project (AUP). It successfully provided quench protection and monitoring (QPM) for a cold superconducting bus test in November 2020. The Mu2e quench detection design has since been implemented for production testing of the AUP magnets. A detailed description of the system along with results from the AUP superconducting bus test will be presented.

monitoring↗
DOE OSTI2021

Information Leakage Analysis using a Co-design-Based Fault Injection Technique on a RISC-V Microprocessor

The RISC-V instruction set architecture open licensing policy has spawned a hive of development activity, making a range of implementations publicly available. The environments in which RISC-V operates have expanded correspondingly, driving the need for a generalized approach to evaluating the reliability of RISC-V implementations under adverse operating conditions or after normal wear-out periods. Fault injection (FI) refers to the process of changing the state of registers or wires, either permanently or momentarily, and then observing execution behavior. The analysis provides insight into the development of countermeasures that protect against the leakage or corruption of sensitive information which might occur because of unexpected execution behavior. In this paper, we develop a hardware-software co-design architecture that enables fast, configurable fault emulation and utilize it for information leakage and data corruption analysis. Modern System-on-chip FPGAs enable building an evaluation platform where control elements run on a processor(s) (PS) simultaneously with the target design running in the programmable logic (PL). Software components of the FI system introduce faults and report execution behavior. A pair of RISC-V FI-instrumented implementations are created and configured to execute the Advanced Encryption Standard and Twister algorithms. Key and plaintext information leakage and degraded pseudo-random sequences are both observed in the output for a subset of the emulated faults.

42 ENGINEERING↗
DOE OSTI2019

A Rotational Control in Medium-Voltage Modular Solid-State Transformer-Based Converter System

This article presents a novel control strategy to significantly reduce the high-frequency transformer loss in a modular solid-state transformer (SST) based converter system. The modular SST design is based on an ac-dc power-electronic building block comprised of an H-bridge at the ac input and a bidirectional soft-switching isolated dc-dc converter with a medium-voltage insulated high-frequency transformer. The ac terminals of input H-bridges are connected in series and directly coupled to the medium-voltage ac line, while the output dc terminals are all connected in parallel at a low voltage. The key innovation described in this paper, without sacrificing the output performance, is the control scheme that reduces core and winding losses associated with the dc-dc resonant stage by turning off the selected dc-dc converters in synchronism with the line voltage. The prototype for the test described in this paper is based on a modular SST where each module is rated at 50 kVA, with a 200 kHz transformer using 1.7 kV silicon carbide discrete mosfets, but the described control concepts are more broadly applicable to similar topologies.

42 ENGINEERING↗
DOE OSTI2015

Analyzing the effectiveness of a frame-level redundancy scrubbing technique for SRAM-based FPGAs

Radiation effects such as soft errors are the major threat to the reliability of SRAM-based FPGAs. This work analyzes the effectiveness in correcting soft errors of a novel scrubbing technique using internal frame redundancy called Frame-level Redundancy Scrubbing (FLR-scrubbing). This correction technique can be implemented in a coarse grain TMR design. The FLR-scrubbing technique was implemented on a mid-size Xilinx Virtex-5 FPGA device used as a case study. The FLR-scrubbing technique was tested under neutron radiation and fault injection. Implementation results demonstrated minimum area and energy consumption overhead when compared to other techniques. The time to repair the fault is also improved by using the Internal Configuration Access Port (ICAP). Lastly, neutron radiation test results demonstrated that the proposed technique is suitable for correcting accumulated SEUs and MBUs.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2020

Design and Testing of the Address in Real-Time Data Driver Card for the Micromegas Detector of the ATLAS New Small Wheel Upgrade

The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data in the Micro-Mesh Gaseous Structure (Micromegas) detector of the ATLAS New Small Wheel (NSW) upgrade. The Address in Real Time (ART) signals are generated by the front-end ASIC, named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and implement the hit-selection. The processed data from the ART ASIC will be transmitted out of the NSW through the GBTx serializer, the unidirectional Versatile Twin Transmitter (VTTx) and fiber optical links. The ART signal is critical for the ATLAS experiment trigger selection thus the performance and stability of the ADDC is very important. To ensure extensive testing of the ADDC, an FPGA Mezzanine Card (FMC) based testing platform and a special designed firmware/software are developed. We find that this test platform works with the commercial Xilinx VC707 FPGA development kit, independent of the other electronics of the NSW it can test all the functions of the ADDC and its long-term stability. This paper will introduce the design, testing procedure and results of the ADDC and the FMC testing platform.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2023

Control System of Multi-Port Autonomous Reconfigurable Solar Power Plant (MARS) & HIL Platforms for Design

Multi-port autonomous reconfigurable solar power plant (MARS) provides an attractive alternative to connect photovoltaic (PV) and energy storage systems (ESSs) to high-voltage direct current (HVdc) links and high-voltage alternating current (ac) grids. In this paper, a unique hierarchical control system of MARS is proposed and evaluated. To evaluate the control system and associated algorithms in early-stage research of complex architectures like MARS, it is important to develop unique suitable hardware-in-the-loop (HIL) platforms. In this paper, the HIL platforms for MARS to evaluate the performance of the hierarchical control system and the control algorithms implemented are presented. Further, they help with the design process of control systems. The real-time simulation models and algorithms that are utilized for MARS in the HIL platforms are also discussed in the paper. The HIL experiments of the control system of MARS showcase the capability to provide continuity of operation under faults and frequency support to the power grid during loss of generation. They also showcase the stability of the proposed hierarchical control system of MARS.

14 SOLAR ENERGY↗
DOE OSTI2025

High-count rate effects in event processing for XRISM/ Resolve X-ray microcalorimeter: I. Ground test

The spectroscopic performance of an X-ray microcalorimeter is compromised at high count rates. We utilize the Resolve X-ray microcalorimeter onboard the XRISM satellite to examine the effects observed during high-count rate measurements and propose modeling approaches to mitigate them. We specifically address the following instrumental effects that impact performance: CPU limit, pile-up, and untriggered electrical cross-talk. Experimental data at high count rates were acquired during ground testing using the flight model instrument and a calibration X-ray source. In the experiment, data processing not limited by the performance of the onboard CPU was run in parallel, which cannot be done in orbit. This makes it possible to access the data degradation caused by limited CPU performance. We use these data to develop models that allow for a more accurate estimation of the aforementioned effects. To illustrate the application of these models in observation planning, we present a simulated observation of GX 13+1. Understanding and addressing these issues is crucial to enhancing the reliability and precision of X-ray spectroscopy in situations characterized by elevated count rates.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Passband Signal Detection at the Edge

Algorithms for radio frequency (RF) spectrum awareness need to be compatible with edge hardware to be practical for many applications. We developed a signal detection and classification model for the ZCU111 RF System-on-a-Chip (RFSoC) that operates on the fast Fourier transform of passband RF data. The system can detect and classify multiple signals of interest and display the predictions in real-time. The model consists of a modified ConvNeXt backbone and YOLOv3 head to operate on the Deep Learning Processing Unit on the RFSoC. We gathered datasets for training and testing by using a software defined radio to transmit example signals of Wi-Fi 802.11 b/g, Wi-Fi 802.11 n, FM Radio, LTE and LTE-M. By leveraging multiple inputs on the RFSoC frontend, the datasets span up to 4 GHz of bandwidth. The models showed high performance in classification accuracy, center frequency error, bandwidth error, and detection accuracy for both single and multi-signal datasets.

42 ENGINEERING↗
DOE OSTI2021

Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle Reconstruction in High Energy Physics

Graph neural networks have been shown to achieve excellent performance for several crucial tasks in particle physics, such as charged particle tracking, jet tagging, and clustering. An important domain for the application of these networks is the FGPA-based first layer of real-time data filtering at the CERN Large Hadron Collider, which has strict latency and resource constraints. We discuss how to design distance-weighted graph networks that can be executed with a latency of less than one μs on an FPGA. To do so, we consider a representative task associated to particle reconstruction and identification in a next-generation calorimeter operating at a particle collider. We use a graph network architecture developed for such purposes, and apply additional simplifications to match the computing constraints of Level-1 trigger systems, including weight quantization. Using the hls4ml library, we convert the compressed models into firmware to be implemented on an FPGA. Performance of the synthesized models is presented both in terms of inference accuracy and resource usage.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Experimental Validation of a Modular All-Electric Power Take-Off Topology for Wave Energy Converter Enabling Marine Renewable Energy Interconnection

Power electronic converters are an enabling technology for the emerging marine energy applications, such as using ocean waves to produce electricity. This paper outlines the power take-off system and its key components used in a wave energy converter offering modularity and scalability to generate power efficiently. The proposed power take-off system was implemented based on a modular multilevel converter and could be deployed to convert any alternating current electrical energy to a different alternating current for interconnection to grid or non-grid applications. Examples of widespread deployment are supplying electricity to coastal communities or producing clean drinking water. The analysis using both the simulation tests and laboratory experiments verified the design objectives and basic functionality of the developed power take-off system. An acceptable response using a field programmable gate array-based controlled laboratory testbench was achieved, complying with guidelines specified in the prevalent industry standards. Seamless operation during steady-state and transients for the studied wave energy converter was achieved as supported by the obtained results. The key findings of this work were experimentally examined under different load conditions, direct current bus voltage fluctuations, and generator speed–torque regulation. The ability of the power take-off system to generate high-power quality of the waveforms, e.g., against adhering to the IEEE 519-2022 standard for total harmonic distortion limits, is also confirmed.

Engineering↗