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NASA NTRS2017

Magnetic Field Sensing with 4H SiC Diodes: N vs P Implantation

We explore the magnetic sensing capabilities of two 4H-SiC n+p diodes fabricated by NASA Glenn which only differ in the implanted ion species, nitrogen and phosphorus, and the implant activation annealing time. We use low- and high-field electrically detected magnetic resonance (EDMR) to investigate the defect structure used to sense magnetic fields as well as to evaluate the sensitivity. In addition, we expose these devices to high energy electron radiation to evaluate the defect sensing capability in a harsh radiation environment. The results from this work will allow us to tailor our processing methods to design a more optimal 4H-SiC pn diode for magnetic field sensing in harsh environments.

Cochrane, Corey J.↗
NASA NTRS1998

Gaseous Etching for Characterization of Structural Defects in Silicon Carbide Single Crystals

Single crystal SiC substrates were subjected to high-temperature H2/C3H8 gaseous etches. The etches resulted in a variety of surface features on 4H-SiC substrates that included elongated hillocks from 10 to more than 100 microns in length by a few microns in width. In some 4H- and 6H-SiC substrates, the etches resulted in a continuous coverage of macrosteps. We conclude that the morphology observed after the etching process is influenced by the local Si-C bilayer stacking sequence on the surface of off-(0001)oriented substrates. A model is presented for the formation of the hillocks, based on localized transformations of the 4H substrates during the high temperature etch process.

Powell, J. A.↗
NASA NTRS2001

Ab-Initio Description and Prediction of Properties of Carbon-Based and Other Non-Metallic Materials

We have resolved the long-standing problem consisting of 30%-50% theoretical underestimates of the band gaps of non-metallic materials. We describe the Bagayoko, Zhao, and Williams (BZW) method that rigorously circumvents the basis-set and variational effect presumed to be a cause of these underestimates. We present ab-initio, computational results that are in agreement with experiment for diamond (C), silicon (Si), silicon carbides (3C-SiC and 4H-SiC), and other semiconductors (GaN, BaTiO3, AlN, ZnSe, ZnO). We illustrate the predictive capability of the BZW method in the case of the newly discovered cubic phase of silicon nitride (c-Si3N4) and of selected carbon nanotabes [(10,0), and (8,4)]. Our conclusion underscores the inescapable need for the BZW method in ab-initio calculations that employ a basis set in a variational approach. Current nanoscale trends amplify this need. We estimate that the potential impact of applications of the BZW method in advancing our understanding of nonmetallic materials, in informing experiment, and particularly in guiding device design and fabrication is simply priceless.

Bagayoko, D.↗
NASA NTRS2002

Method for Growing Low-Defect Single Crystal Heteroepitaxial Films

A method is disclosed for growing high-quality low-defect crystal films heteroepitaxially on substrates that are different than the crystal films. The growth of the first two heteroepitaxial bilayers is performed on a first two-dimensional nucleate island before a second growth of two-dimensional nucleation is allowed to start. The method is particularly suited for the growth of 3C-SiC, 2H-AlN, or 2H-GaN on 6H-SiC, 4H-SiC, or silicon substrates.

Powell, J. Anthony↗
NASA NTRS2002

Growth of Defect-Free 3C-Sic on 4H- and 6H-SIC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3C-SiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (Delta/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗
NASA NTRS2004

Measurement of Thin Film Integrated Passive Devices on SiC through 500 C

Wireless communication in jet engines and high temperature industrial applications requires FD integrated circuits (RFICs) on wide bandgap semiconductors such as Silicon Carbide (SiC). In this paper, thin-film NiCr resistors, MIM capacitors, and spiral inductors are fabricated on a high purity semi-insulating 4H-SiC substrate. The devices are experimentally characterized through 50 GHz at temperatures of up to 500 C and the equivalent circuits are deembedded from the measured data. It is shown that the NiCr resistors are stable within 10% to 300 C while the capacitors have a value stable within 10% through 500 C.

Schwartz, Zachary D.↗
NASA NTRS2004

Growth and Characterization of Silicon-Carbide Hetero-Polytype Structures

Films discussed in this repok were deposited at NASA Glenn Research Center on on- orientation 4H-Sic substrates. Substrates were patterned in order to form mesa structures of different shapes and sizes. The nominal thickness of the 3C-Sic film was approximately 10 microns although the thickness could change considerably between defect-free and defected mesa structures. The primary objective was to identify defect structures in defect-free mesas and in particular determine the degree and mode of strain relaxation in 3C films with thickness exceeding critical thickness.

Skowronski, Marek↗
NASA NTRS2005

Static and Turn-on Switching Characteristics of 4H-Silicon Carbide SITs to 200 deg C

Test results are presented for normally-off 4H-SiC Static Induction Transistors (SITs) intended for power switching and are among the first normally-off such devices realized in SiC. At zero gate bias, the gate p-n junction depletion layers extend far enough into the conduction channel to cut off the channel. Application of forward gate bias narrows the depletion regions, opening up the channel to conduction by majority carriers. In the present devices, narrow vertical channels get pinched by depletion regions from opposite sides. Since the material is SiC, the devices are usable at temperatures above 150 C. Static curve and pulse mode switching observations were done at selected temperatures up to 200 C on a device with average static characteristics from a batch of similar devices. Gate and drain currents were limited to about 400 mA and 3.5 A, respectively. The drain voltage was limited to roughly 300 V, which is conservative for this 600 V rated device. At 23 C, 1 kW, or even more, could be pulse mode switched in 65 ns (10 to 90 percent) into a 100 load. But at 200 C, the switching capability is greatly reduced in large part by the excessive gate current required. Severe collapse of the saturated drain-to-source current was observed at 200 C. The relation of this property to channel mobility is reviewed.

Niedra, Janis M.↗
NASA NTRS2005

Improved Method of Manufacturing SiC Devices

The phrase, "common-layered architecture for semiconductor silicon carbide" ("CLASSiC") denotes a method of batch fabrication of microelectromechanical and semiconductor devices from bulk silicon carbide. CLASSiC is the latest in a series of related methods developed in recent years in continuing efforts to standardize SiC-fabrication processes. CLASSiC encompasses both institutional and technological innovations that can be exploited separately or in combination to make the manufacture of SiC devices more economical. Examples of such devices are piezoresistive pressure sensors, strain gauges, vibration sensors, and turbulence-intensity sensors for use in harsh environments (e.g., high-temperature, high-pressure, corrosive atmospheres). The institutional innovation is to manufacture devices for different customers (individuals, companies, and/or other entities) simultaneously in the same batch. This innovation is based on utilization of the capability for fabrication, on the same substrate, of multiple SiC devices having different functionalities (see figure). Multiple customers can purchase shares of the area on the same substrate, each customer s share being apportioned according to the customer s production-volume requirement. This makes it possible for multiple customers to share costs in a common foundry, so that the capital equipment cost per customer in the inherently low-volume SiC-product market can be reduced significantly. One of the technological innovations is a five-mask process that is based on an established set of process design rules. The rules provide for standardization of the fabrication process, yet are flexible enough to enable multiple customers to lay out masks for their portions of the SiC substrate to provide for simultaneous batch fabrication of their various devices. In a related prior method, denoted multi-user fabrication in silicon carbide (MUSiC), the fabrication process is based largely on surface micromachining of poly SiC. However, in MUSiC one cannot exploit the superior sensing, thermomechanical, and electrical properties of single-crystal 6H-SiC or 4H-SiC. As a complement to MUSiC, the CLASSiC five-mask process can be utilized to fabricate multiple devices in bulk single-crystal SiC of any polytype. The five-mask process makes fabrication less complex because it eliminates the need for large-area deposition and removal of sacrificial material. Other innovations in CLASSiC pertain to selective etching of indium tin oxide and aluminum in connection with multilayer metallization. One major characteristic of bulk micromachined microelectromechanical devices is the presence of three-dimensional (3D) structures. Any 3D recesses that already exist at a given step in a fabrication process usually make it difficult to apply a planar coat of photoresist for metallization and other subsequent process steps. To overcome this difficulty, the CLASSiC process includes a reversal of part of the conventional flow: Metallization is performed before the recesses are etched.

Okojie, Robert S.↗
NASA NTRS2001

Growth of Defect-Free 3C-SiC on 4H- and 6H-SiC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3CSiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (delta a/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗
NASA NTRS2001

Homoepitaxial "Web Growth" of SiC to Terminate C-Axis Screw Dislocations and Enlarge Step-Free Surfaces

Homoepitaxial CVD growth of thin lateral cantilevers emanating from the edges of mesa patterns dry-etched into on-axis commercial 4H-SiC substrates prior to growth is reported. Cantilevers on the order of a micrometer thick extending tens of micrometers from the edge of a mesa have been grown. The termination of vertically propagating screw dislocations, including a micropipe, that are overgrown by the cantilevers has been demonstrated, in large part because the crystal structure of the cantilevers is established laterally from the mesa sidewalls. This technique could help reduce performance-degrading dislocations in SiC electrical devices.

Neudeck, Philip G.↗
NASA NTRS2016

Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

Ikpe, Stanley A.↗
NASA NTRS2016

800 C Silicon Carbide (SiC) Pressure Sensors for Engine Ground Testing

MEMS-based 4H-SiC piezoresistive pressure sensors have been demonstrated at 800 C, leading to the discovery of strain sensitivity recovery with increasing temperatures above 400 C, eventually achieving up to, or near, 100 recovery of the room temperature values at 800 C. This result will allow the insertion of highly sensitive pressure sensors closer to jet, rocket, and hypersonic engine combustion chambers to improve the quantification accuracy of combustor dynamics, performance, and increase safety margin. Also, by operating at higher temperature and locating closer to the combustion chamber, reduction of the length (weight) of pressure tubes that are currently used will be achieved. This will result in reduced costlb to access space.

Pressure sensors↗
NASA NTRS2017

Novel High Temperature Capacitive Pressure Sensor Utilizing SiC Integrated Circuit Twin Ring Oscillators

This paper describes initial development and testing of a novel high temperature capacitive pressure sensor system. The pressure sensor system consists of two 4H-SiC 11-stage ring oscillators and a SiCN capacitive pressure sensor. One oscillator has the capacitive pressure sensor fixed at one node in its feedback loop and varies as a function of pressure and temperature while the other provides a pressure-independent reference frequency which can be used to temperature compensate the output of the first oscillator. A two-day repeatability test was performed up to 500C on the oscillators and the oscillator fundamental frequency changed by only 1. The SiCN capacitive pressure sensor was characterized at room temperature from 0 to 300 psi. The sensor had an initial capacitance of 3.76 pF at 0 psi and 1.75 pF at 300 psi corresponding to a 54 change in capacitance. The integrated pressure sensor system was characterized from 0 to 300 psi in steps of 50 psi over a temperature range of 25 to 500C. The pressure sensor system sensitivity was 0.113 kHzpsi at 25C and 0.026 kHzpsi at 500C.

high temperature↗
NASA NTRS2016

Heavy Ion Induced Degradation in SiC Schottky Diodes: Bias and Energy Deposition Dependence

Experimental results on ion-induced leakage current increase in 4H-SiC Schottky power diodes are presented. Monte Carlo and TCAD simulations show that degradation is due to the synergy between applied bias and ion energy deposition. This degradation is possibly related to thermal spot annealing at the metal semiconductor interface. This thermal annealing leads to an inhomogeneity of the Schottky barrier that could be responsible for the increase leakage current as a function of fluence.

modeling↗
NASA NTRS2017

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Silicon Carbid↗
NASA NTRS2016

A Discrete Component Low-Noise Preamplifier Readout for a Linear (1x16) SiC Photodiode Array

A compact, low-noise and inexpensive preamplifier circuit has been designed and fabricated to optimally readout a common cathode (1x16) channel 4H-SiC Schottky photodiode array for use in ultraviolet experiments. The readout uses an operational amplifier with 10 pF capacitor in the feedback loop in parallel with a low leakage switch for each of the channels. This circuit configuration allows for reiterative sample, integrate and reset. A sampling technique is given to remove Johnson noise, enabling a femtoampere level readout noise performance. Commercial-off-the-shelf acquisition electronics are used to digitize the preamplifier analogue signals. The data logging acquisition electronics has a different integration circuit, which allows the bandwidth and gain to be independently adjusted. Using this readout, photoresponse measurements across the array between spectral wavelengths 200 nm and 370 nm are made to establish the array pixels external quantum efficiency, current responsivity and noise equivalent power.

low-noise preamplifier↗
NASA NTRS2017

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Spry, David J.↗