Search NASA⌕ Search

SEARCH · Search NASA

Results for “ADC”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

Converting the Active Digital Controller for Use in Two Tests

The Active Digital Controller is a system used to control the various functions of wind tunnel models. It has the capability of digitizing and saving of up to sixty-four channels of analog data. It can output up to 16 channels of analog command signals. In addition to its use as a general controller, it can run up to two distinct control laws. All of this is done at a regulated speed of two hundred hertz. The Active Digital Controller (ADC) was modified for use in the Actively Controlled Response of Buffet Affected Tails (ACROBAT) tests and for side-wall pressure data acquisition. The changes included general maintenance and updating of the controller as well as setting up special modes of operation. The ACROBAT tests required that two sets of output signals be available. The pressure data acquisition needed a sampling rate of four hundred hertz, twice the standard ADC rate. These modifications were carried out and the ADC was used during the ACROBAT wind tunnel entry.

Wright, Robert G.↗
NASA NTRS2004

Benchmarking Memory Performance with the Data Cube Operator

Data movement across a computer memory hierarchy and across computational grids is known to be a limiting factor for applications processing large data sets. We use the Data Cube Operator on an Arithmetic Data Set, called ADC, to benchmark capabilities of computers and of computational grids to handle large distributed data sets. We present a prototype implementation of a parallel algorithm for computation of the operatol: The algorithm follows a known approach for computing views from the smallest parent. The ADC stresses all levels of grid memory and storage by producing some of 2d views of an Arithmetic Data Set of d-tuples described by a small number of integers. We control data intensity of the ADC by selecting the tuple parameters, the sizes of the views, and the number of realized views. Benchmarking results of memory performance of a number of computer architectures and of a small computational grid are presented.

Frumkin, Michael A.↗
NASA NTRS1985

In vivo inhibition of polyamine biosynthesis and growth in tobacco ovary tissues

Post fertilization growth of tobacco ovary tissues treated with inhibitors of polyamine (PA) biosynthesis was examined in relation to endogenous PA titers and the activities of arginine decarboxylase (ADC, EC 4.1.1.19) and ornithine decarboxylase (ODC, EC 4.1.1.17). DL-alpha-Difluoromethylornithine (DFMO) and DL-alpha-difluoromethylarginine (DFMA), specific, irreversible ("suicide") inhibitors of ODC and ADC in vitro, were used to modulate PA biosynthesis in excised flowers. ODC represented >99% of the total decarboxylase activity in tobacco ovaries. In vivo inhibition of ODC with DFMO resulted in a significant decrease in PA titers, ovary fresh weight and protein content. Simultaneous inhibition of both decarboxylases by DFMO and DFMA produced only a marginally greater depression in growth and PA titers, indicating that ODC activity is rate-limiting for PA biosynthesis in these tissues. Paradoxically, DFMA alone inhibited PA biosynthesis, not as a result of a specific inhibition of ADC, but primarily through the inactivation of ODC. In vivo inhibition of ODC by DFMA appears to result from arginase-mediated hydrolysis of this inhibitor to urea and DFMO, the suicide substrate for ODC. Putrescine conjugates in tobacco appear to function as a storage form of this amine which, upon hydrolysis, may contribute to Put homeostasis during growth.

NASA Program Space Biology↗
NASA NTRS2008

Customizable Digital Receivers for Radar

Compact, highly customizable digital receivers are being developed for the system described in 'Radar Interferometer for Topographic Mapping of Glaciers and Ice Sheets' (NPO-43962), NASA Tech Briefs, Vol. 31, No. 7 (August 2007), page 72. The receivers are required to operate in unison, sampling radar returns received by the antenna elements in a digital beam-forming (DBF) mode. The design of these receivers could also be adapted to commercial radar systems. At the time of reporting the information for this article, there were no commercially available digital receivers capable of satisfying all of the operational requirements and compact enough to be mounted directly on the antenna elements. A provided figure depicts the overall system of which the digital receivers are parts. Each digital receiver includes an analog-to-digital converter (ADC), a demultiplexer (DMUX), and a field-programmable gate array (FPGA). The ADC effects 10-bit band-pass sampling of input signals having frequencies up to 3.5 GHz. The input samples are demultiplexed at a user-selectable rate of 1:2 or 1:4, then buffered in part of the FPGA that functions as a first-in/first-out (FIFO) memory. Another part of the FPGA serves as a controller for the ADC, DMUX, and FIFO memory and as an interface between (1) the rest of the receiver and (2) a front-panel data port (FPDP) bus, which is an industry-standard parallel data bus that has a high data-rate capability and multichannel configuration suitable for DBF. Still other parts of the FPGA in each receiver perform signal-processing functions. The digital receivers can be configured to operate in a stand-alone mode, or in a multichannel mode as needed for DBF. The customizability of the receiver makes it applicable to a broad range of system architectures. The capability for operation of receivers in either a stand-alone or a DBF mode enables the use of the receivers in an unprecedentedly wide variety of radar systems.

Moller, Delwyn↗
NASA NTRS2012

High fidelity, radiation tolerant analog-to-digital converters

Techniques for an analog-to-digital converter (ADC) using pipeline architecture includes a linearization technique for a spurious-free dynamic range (SFDR) over 80 deciBels. In some embodiments, sampling rates exceed a megahertz. According to a second approach, a switched-capacitor circuit is configured for correct operation in a high radiation environment. In one embodiment, the combination yields high fidelity ADC (>88 deciBel SFDR) while sampling at 5 megahertz sampling rates and consuming <60 milliWatts. Furthermore, even though it is manufactured in a commercial 0.25-.mu.m CMOS technology (1 .mu.m=12.sup.-6 meters), it maintains this performance in harsh radiation environments. Specifically, the stated performance is sustained through a highest tested 2 megarad(Si) total dose, and the ADC displays no latchup up to a highest tested linear energy transfer of 63 million electron Volts square centimeters per milligram at elevated temperature (131 degrees C.) and supply (2.7 Volts, versus 2.5 Volts nominal).

Wang, Charles Chang-I↗
NASA NTRS2012

Auto Code Generation for Simulink-Based Attitude Determination Control System

This paper details the work done to auto generate C code from a Simulink-Based Attitude Determination Control System (ADCS) to be used in target platforms. NASA Marshall Engineers have developed an ADCS Simulink simulation to be used as a component for the flight software of a satellite. This generated code can be used for carrying out Hardware in the loop testing of components for a satellite in a convenient manner with easily tunable parameters. Due to the nature of the embedded hardware components such as microcontrollers, this simulation code cannot be used directly, as it is, on the target platform and must first be converted into C code; this process is known as auto code generation. In order to generate C code from this simulation; it must be modified to follow specific standards set in place by the auto code generation process. Some of these modifications include changing certain simulation models into their atomic representations which can bring new complications into the simulation. The execution order of these models can change based on these modifications. Great care must be taken in order to maintain a working simulation that can also be used for auto code generation. After modifying the ADCS simulation for the auto code generation process, it is shown that the difference between the output data of the former and that of the latter is between acceptable bounds. Thus, it can be said that the process is a success since all the output requirements are met. Based on these results, it can be argued that this generated C code can be effectively used by any desired platform as long as it follows the specific memory requirements established in the Simulink Model.

MolinaFraticelli, Jose Carlos↗
NASA NTRS2011

Characterization of High-Speed IF Digitizers for Use by NASA Deep Space Network

My project primarily focused on the evaluation of several candidate converters to determine which provides the best overall performance for the needs of the DSCC Downlink Array (DDA). Of particular concern was the flatness of the gain and group delay of the converter over the Intermediate Frequency (IF) bandwidth, as excessive variation interferes with the beam forming that occurs when combining the signals from many antennas. In addition, converter nonlinearity and noise were evaluated as these could limit the DDA's ability to resolve weak signals, particularly in the presence of large interferers. The sensitivity of the noise at the output of the converters due to noise in the power supplies and jitter in the analog-to-digital converters (ADC) and the reference clock were also evaluated. Specifically, I worked with various high speed (1280 to 2000 megahertz sampling clock) ADCs.

analog-to-digital converters (ADC)↗
NASA NTRSDate not supplied

Radiation-Hard Parallel Readout Circuit for Low-Frequency Voltage Signal Measurements

NASA Goddard Space Flight Center (GSFC) has successfully developed and tested a custom-designed low-noise multi-channel digitizer (MCD) application specific integrated circuit (ASIC) for operation in harsh radiation environments. The MCD-ASIC is optimized for low-frequency and low-voltage signal measurements from sensors and transducers. It has 20 input channels where each channel is comprised of auto-zeroed chopper variable-gain amplifier, post amplifier, and a second order ∑∆ modulator. ∑∆ analog-to-digital converter (ADC) relies on oversampling and noise shaping to achieve high-resolution conversion. However, the MCD-ASIC requires digital filtering and decimation to convert the output single bit streams from the ADC to useful data words. A parallel digital platform such as a field-programmable-gate-array (FPGA) is highly suitable to fully leverage the capabilities of the MCD-ASIC. The FPGA controls the MCD-ASIC via serial peripheral interface (SPI) protocol and acquires data from it. A Python-script communicates with the FPGA board through a USB interface on a cross operating platform. Using this architecture, the system is capable of monitoring up to 20 voltage readout channels simultaneously in a real-time manner. Each channel’s parameters can be programmed independently allowing maximum user versatility. In this paper, we present analysis of the analog front-end, the implementation of the digital processing unit on the FPGA, and provide noise performance results from the MCD-ASIC readout.

ASIC↗
NASA NTRSDate not supplied

Attitude Control Approach for Solar Cruiser, a Large, Deep Space Solar Sail

Solar Cruiser is a small satellite Technology Demonstration Mission (TDM) to mature solar sail propulsion technology using a solar sail larger than 1600 square meters, demonstrating performance as a propulsion system and a stable pointing platform for science observations in an artificial halo orbit sunward of the Sun-Earth Lagrange Point 1 (sub-L1). For the “sailcraft” to meet mission ob- jectives, there are several unique attitude control challenges that the Attitude De- termination and Control System (ADCS) must overcome. Large disturbance tor- ques, primarily due to sail deformations coupled with off-sun pointing angles, make it more difficult to maintain adequate controls performance and manage accumulated momentum on the control actuators. The large-amplitude, low- frequency flexible body modes of the sail, in concert with noisy sensors and ac- tuators, make it challenging to mitigate control-structure interactions and main- tain fine pointing capabilities. Stability and control performance during sail de- ployment is complicated by rapidly and widely varying inertias. The Solar Cruiser ADCS effectively addresses these challenges using a simple, traditional control system – including momentum management actuators that use bang- bang control to constrain internal accumulated momentum, a low-pass controls filter and an attitude determination Kalman Filter (KF) that blends multiple star tracker solutions, and a reaction wheel assembly (RWA) with controller gains tuned to specific configurations or inertias. Solar Cruiser’s attitude control ap- proach, and lessons learned from its development, establishes a state of the art of high value to future solar sail missions and other small spacecraft with large de- ployable structures operating in deep space.

solar sail↗
NASA NTRSDate not supplied

Attitude Control Approach for Solar Cruiser, a Large, Deep Space Solar Sail

Solar Cruiser is a small satellite Technology Demonstration Mission (TDM) to mature solar sail propulsion technology using a solar sail larger than 1600 square meters, demonstrating performance as a propulsion system and a stable pointing platform for science observations in an artificial halo orbit sunward of the Sun-Earth Lagrange Point 1 (sub-L1). For the “sailcraft” to meet mission objectives, there are several unique attitude control challenges that the Attitude Determination and Control System (ADCS) must overcome. Large disturbance torques, primarily due to sail deformations coupled with off-sun pointing angles, make it more difficult to maintain adequate controls performance and manage accumulated momentum on the control actuators. The large-amplitude, low-frequency flexible body modes of the sail, in concert with noisy sensors and actuators, make it challenging to mitigate control-structure interactions and maintain fine pointing capabilities. Stability and control performance during sail deployment is complicated by rapidly and widely varying inertias. The Solar Cruiser ADCS effectively addresses these challenges using a simple, traditional control system – including momentum management actuators that use bang-bang control to constrain internal accumulated momentum, a low-pass controls filter and an attitude determination Kalman Filter (KF) that blends multiple star tracker solutions, and a reaction wheel assembly (RWA) with controller gains tuned to specific configurations or inertias. Solar Cruiser’s attitude control approach, and lessons learned from its development, establishes a state of the art of high value to future solar sail missions and other small spacecraft with large deployable structures operating in deep space.

solar sail↗
DOE OSTI2024

Jamming Detection for Low-Resolution SC-FDE Systems: A Machine Learning Approach

Jammers interfere with communication between base stations (BSs) and legitimate users, leading to degradation of wireless system performance. Our study focuses on jamming detection for wideband single-carrier frequency domain equalization (SC-FDE) systems with low-resolution analog-to digital converters (ADCs). In such systems, jamming detection is challenging because traditional analytical approaches cannot be directly applied due to the delay dispersion in wideband channels and the non-linearity induced by low-resolution ADCs. We propose a machine learning (ML)-based jamming detection method that directly uses the quantized receive signals. Significantly, our ML-based detector can be integrated into existing standard frameworks, such as unique word (UW)-based SC-FDE systems, as it uses existing pilots without requiring additional pilots for jamming detection. Through numerical simulations, we show that two or more bits provide satisfactory performance compared to unquantized scenarios. Additionally, we demonstrate that using more and well-separated pilot symbols improves performance.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2025

Design of an 8-channel 40 GS/s 20 mW/Ch waveform sampling ASIC in 65 nm CMOS

One picosecond timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in TSMC 65 nm process targetting one picosecond resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing for picosecond time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC. PSEC5 has been submitted for fabrication.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Synergistic effects of Pd single atoms and nanoclusters boosting SnO 2 gas sensing performance

Tin(IV) oxide-supported Pd is a promising heterogenous catalyst for CO oxidation relevant for environmental cleanup reactions. In this study, an atomically dispersed Pd catalyst on SnO 2 (ADC Pd/SnO 2 ) hybrid material is successfully synthesized via a straightforward wet chemistry method and is found to exhibit superior performance toward CO sensing. Ex situ EXAFS analysis confirms the formation of single Pd atoms and small Pd nanoclusters stabilized on the SnO 2 (110) surface. Further, the material exhibits high efficiency in generating adsorbed O 2 - as well as high activity in catalyzing CO oxidation at low temperatures, resulting in exceptional sensitivity and selectivity toward CO in comparison to pure SnO 2 and Pd nanoparticles loaded on SnO 2 respectively. In situ FTIR measurements unravel CO adsorption kinetics on ADC Pd/SnO 2 under reaction conditions, and a possible sensing mechanism is put forth in which CO is transformed into CO 2 by reaction with active oxygen species; and concurrently, carbon-related species (bicarbonates and carbonates) are formed and decomposed into CO 2 .

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2026

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗
DOE OSTI2025

SALSA: a new versatile readout chip for MPGD detectors

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. In conclusion, the final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.

Data processing↗
DOE OSTI2024

In vitro evidence that the vasorelaxant effects of 2‐nitro‐1‐phenyl‐1‐propanol on rat coronary arteries involve cyclic nucleotide pathways

Abstract The synthetic nitro‐alcohol 2‐nitro‐1‐phenyl‐1‐propanol (NPP) has endothelium‐independent relaxing properties in isolated preparations of rat aorta and mesenteric artery. In this study, we investigated whether the vasodilator effects occur in coronary vessels and explored whether hyperpolarization is involved in the underlying mechanism of NPP‐induced smooth muscle relaxation. The relaxing responses were studied in isolated preparations of the left anterior descending coronary (ADC) and the septal coronary (SC) arteries, which had been previously maintained under sustained contraction induced by the thromboxane A 2 analogue U‐46619. Administered cumulatively, NPP elicited concentration‐dependent vasorelaxation with similar potency in both vessels. The relaxant effect remained unaffected by the nitric oxide synthase inhibitor L‐NAME, the protein kinase C inhibitor bisindolylmaleimide IV and the Rho‐associated protein kinase inhibitor Y‐27632. However, it was significantly diminished by the adenylyl cyclase inhibitor MDL‐12,330A, the guanylyl cyclase inhibitor ODQ, as well as the K + channel inhibitors tetraethylammonium and CsCl. In ADC preparations impaled with intracellular micropipettes, NPP hyperpolarized the vascular preparation. When the isolated preparation was precontracted by 5‐hydroxytryptamine or 80 mM KCl, NPP‐induced relaxation with lower pharmacological potency compared to the vessels contracted by U‐46619. In conclusion, NPP exhibits vasorelaxant effects on rat coronary arteries, likely involving pathways that include cyclic nucleotide production and membrane hyperpolarization.

Vasconcelos‐Silva, Alfredo Augusto↗
DOE OSTI2026

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗
DOE OSTI2025

Design of Digital Acquisition for Beam Current Monitor

As a part of the Proton Improvement Plan II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, Turner [Fermilab] (ORCID:0009000348159256)↗