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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1978

Contour Detector and Data Acquisition System for the Left Ventricular Outline

A real-time contour detector and data acquisition system is described for an angiographic apparatus having a video scanner for converting an X-ray image of a structure characterized by a change in brightness level compared with its surrounding into video format and displaying the X-ray image in recurring video fields. The real-time contour detector and data acqusition system includes track and hold circuits; a reference level analog computer circuit; an analog compartor; a digital processor; a field memory; and a computer interface.

Reiber, J. H. C.↗
NASA NTRS1977

TVC actuator model

A prototype Space Shuttle Main Engine (SSME) Thrust Vector Control (TVC) Actuator analog model was successfully completed. The prototype, mounted on five printed circuit (PC) boards, was delivered to NASA, checked out and tested using a modular replacement technique on an analog computer. In all cases, the prototype model performed within the recording techniques of the analog computer which is well within the tolerances of the specifications.

Baslock, R. W.↗
NASA NTRS2007

Analog Nonvolatile Computer Memory Circuits

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

MacLeod, Todd↗
NASA NTRS1988

A direct-execution parallel architecture for the Advanced Continuous Simulation Language (ACSL)

A direct-execution parallel architecture for the Advanced Continuous Simulation Language (ACSL) is presented which overcomes the traditional disadvantages of simulations executed on a digital computer. The incorporation of parallel processing allows the mapping of simulations into a digital computer to be done in the same inherently parallel manner as they are currently mapped onto an analog computer. The direct-execution format maximizes the efficiency of the executed code since the need for a high level language compiler is eliminated. Resolution is greatly increased over that which is available with an analog computer without the sacrifice in execution speed normally expected with digitial computer simulations. Although this report covers all aspects of the new architecture, key emphasis is placed on the processing element configuration and the microprogramming of the ACLS constructs. The execution times for all ACLS constructs are computed using a model of a processing element based on the AMD 29000 CPU and the AMD 29027 FPU. The increase in execution speed provided by parallel processing is exemplified by comparing the derived execution times of two ACSL programs with the execution times for the same programs executed on a similar sequential architecture.

Carroll, Chester C.↗
DOE OSTI2025

Nonlinear analog processing with anisotropic nonlinear films

Digital signal processing is the cornerstone of several modern-day technologies, yet in multiple applications it faces critical bottlenecks related to memory and speed constraints. Thanks to recent advances in metasurface design and fabrication, light-based analog computing has emerged as a viable option to partially replace or augment digital approaches. Several light-based analog computing functionalities have been demonstrated using patterned flat optical elements, with great opportunities for integration in compact nanophotonic systems. So far, however, the available operations have been restricted to the linear regime, limiting the impact of this technology to a compactification of Fourier optics systems. In this paper, we introduce nonlinear operations to the field of metasurface-based analog optical processing, demonstrating that nonlinear optical phenomena, combined with nonlocality in flat optics, can be leveraged to synthesize kernels beyond linear Fourier optics, paving the way to a broad range of new opportunities. As a practical demonstration, we report the experimental synthesis of a class of nonlinear operations that can be used to realize broadband, polarization-selective analog-domain edge detection.

analog image processing↗
NASA NTRS1951

Analysis of Experimental Sea-level Transient Data and Analog Method of Obtaining Altitude Response for Turbine-propeller Engine with Relay-type Speed Control

Correlation has been established between transient engine and control data obtained experimentally and data obtained by simulating the engine and control with an analog computer. This correlation was established at sea-level conditions for a turbine-propeller engine with a relay-type speed control. The behavior of the controlled engine at altitudes of 20,000 and 35,000 feet was determined with an analog computer using the altitude pressure and temperature generalization factors to calculate the new engine constants for these altitudes. Because the engine response varies considerably at altitude some type of compensation appears desirable and four methods of compensation are discussed.

ENGINES, CONTROL↗
NASA NTRS1961

Design and Flight Tests of an Adaptive Control System Employing Normal-Acceleration Command

An adaptive control system employing normal-acceleration command has been designed with the aid of an analog computer and has been flight tested. The design of the system was based on the concept of using a mathematical model in combination with a high gain and a limiter. The study was undertaken to investigate the application of a system of this type to the task of maintaining nearly constant dynamic longitudinal response of a piloted airplane over the flight envelope without relying on air data measurements for gain adjustment. The range of flight conditions investigated was between Mach numbers of 0.36 and 1.15 and altitudes of 10,000 and 40,000 feet. The final adaptive system configuration was derived from analog computer tests, in which the physical airplane control system and much of the control circuitry were included in the loop. The method employed to generate the feedback signals resulted in a model whose characteristics varied somewhat with changes in flight condition. Flight results showed that the system limited the variation in longitudinal natural frequency of the adaptive airplane to about half that of the basic airplane and that, for the subsonic cases, the damping ratio was maintained between 0.56 and 0.69. The system also automatically compensated for the transonic trim change. Objectionable features of the system were an exaggerated sensitivity of pitch attitude to gust disturbances, abnormally large pitch attitude response for a given pilot input at low speeds, and an initial delay in normal-acceleration response to pilot control at all flight conditions. The adaptive system chatter of +/-0.05 to +/-0.10 of elevon at about 9 cycles per second (resulting in a maximum airplane normal-acceleration response of from +/-0.025 g to +/- 0.035 g) was considered by the pilots to be mildly objectionable but tolerable.

McNeill, Water E.↗
DOE OSTI2026

Analog and symbolic computation through the Koopman framework

We develop a Koopman operator framework for studying the computational structure of dynamical systems. Specifically, we show that the resolvent of the Koopman operator provides a natural abstraction of halting, yielding a ‘Koopman halting problem’ that is recursively enumerable in general. For symbolic systems, such as those defined on Cantor space, this operator formulation captures reachability between clopen sets, while for equicontinuous systems we prove that the Koopman halting problem is decidable. Our framework demonstrates that absorbing (halting) states in coarse-grained finite automata correspond to Koopman eigenfunctions with eigenvalue one, while cycles in the transition graph impose spectral constraints associated with periodic dynamics. These results provide a unifying perspective on computation in symbolic and analog systems, showing how computational universality is reflected in operator spectra, invariant subspaces, and algebraic structures. Beyond symbolic dynamics, this operator-theoretic lens opens pathways to analyze the computational properties of a broader class of dynamical systems, including polynomial and analog models, and suggests that computational hardness may admit dynamical signatures in terms of Koopman spectral structure.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS1974

An experimental study of a hybrid adaptive control system

A Liapunov type model reference adaptive control system with five adjustable gains is implemented using a PDP-11 digital computer and an EAI 380 analog computer. The plant controlled is a laboratory type dc servo system. It is made to follow closely a second order linear model. The experimental results demonstrate the feasibility of implementing this rather complex design using only a minicomputer and a reasonable number of operational amplifiers. Also, it points out that satisfactory performance can be achieved even when certain assumptions necessary for the theory are not satisfied.

Lizewski, E. F.↗
NASA NTRS1986

Ab initio study of the ground state surface of Cu3

The ground state surface of the metallic trimer Cu3 is investigated theoretically. Relativistic and correlation effects are taken into account in ab initio computations, which are calibrated against analogous computations for the 1Sigma(g)+ state of Cu2; the results are presented in tables and analyzed. The Cu3 ground state is found to have a 2B2 C(2v) structure with angle greater than 60 deg, lying 59/cm below a 2A1 C(2v) geometry and 280/cm below the D(3h) equilateral geometry. These findings are shown to be in good agreement with the experimental measurements of Rohlfing and Valentini (1986) and their analysis (in terms of a Jahn-Teller distortion of 2E-prime equilateral-triangle geometry) by Truhlar et al. (1986).

Langhoff, Stephen R.↗