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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2003

Strategy-Enhanced Interactive Proving and Arithmetic Simplification for PVS

We describe an approach to strategy-based proving for improved interactive deduction in specialized domains. An experimental package of strategies (tactics) and support functions called Manip has been developed for PVS to reduce the tedium of arithmetic manipulation. Included are strategies aimed at algebraic simplification of real-valued expressions. A general deduction architecture is described in which domain-specific strategies, such as those for algebraic manipulation, are supported by more generic features, such as term-access techniques applicable in arbitrary settings. An extended expression language provides access to subterms within a sequent.

DiVito, Ben L.↗
DOE OSTI2025

Efficient Floating-Point Arithmetic on Fault-Tolerant Quantum Computers

We propose a novel floating-point encoding scheme that builds on prior work involving fixed-point encodings. We encode floating-point numbers using Two's Complement fixed-point mantissas and Two's Complement integral exponents. We used our proposed approach to develop quantum algorithms for fundamental arithmetic operations, such as bit-shifting, reciprocation, multiplication, and addition. We prototyped and investigated the performance of the floating-point encoding scheme on quantum computer simulations by performing reciprocation on randomly drawn inputs and by solving first-order ordinary differential equations, while varying the number of qubits in the encoding. We observed rapid convergence to the exact solutions as we increased the number of qubits and a significant reduction in the number of ancilla qubits required for reciprocation when compared with similar approaches.

Serrallés, José Cruz [Weill Cornell Med. Coll.]↗
NASA NTRS1995

Bit-Wise Arithmetic Coding for Data Compression

Consider the problem of compressing a uniformly quantized source. A traditional approach is to assign variable length codewords to the quantizer output symbols or groups of symbols. Here an alternate solution is proposed: assign a fixed length binary codeword to each output symbol in such a way that a zero is more likely than a one in every codeword bit position. The encoding procedure is described.

Arithmetic↗
NASA NTRS1966

Subroutine allows easy computation in extended precision arithmetic

Subroutine called NPREC allows relatively simple computation of very large numbers or very small fractions with extreme accuracy. This subroutine handles numbers that consist of 35 binary bits /1 word/ for the exponent and 70 bits /2 words/ for the fraction.

Berggren, R. L.↗
NASA NTRS1972

Significance arithmetic experimental package (SIGPAC)

Method for use by computing facility to determine accuracy of computer calculations is presented. Primary goals of error analysis program are described. Program is designed for both FORTRAN 4 and ASSEMBLER for use with IBM 360 computer.

Cole, I.↗
NASA NTRS1977

Fast arithmetic in MacLISP

MacLISP provides a compiler which produces numerical code competitive in speed with some FORTRAN implementations and yet compatible with the rest of the MacLISP system. All numerical programs can be run under the MacLISP interpreter. Additional declarations to the compiler specify type information which allows the generation of optimized numerical code which generally does not require the garbage collection of temporary numerical results. Array accesses are almost as fast as in FORTRAN, and permit the use of dynamically allocated arrays of varying dimensions. The implementation decisions regarding user interface, data representations, and interfacing conventions are discussed which allow the generation of fast numerical LISP code.

Steele, G. L., Jr.↗
NASA NTRS1975

The realization of arithmetic processors for delta modulation encoded signals

The design and realization of digital devices which add or multiply delta modulation (DM) encoded signals are presented. These systems operate directly on the DM bit stream. It is shown that the devices can be constructed using standard digital hardware and that the hardware complexity needed to add or multiply the two DM encoded signals is equivalent to that needed for pulse code modulation (PCM) signals. Experimental results are presented showing the operation of these systems. The results obtained by adding or multiplying DM encoded signals are compared with those obtained using PCM encoded signals on the basis of signal-to-noise ratio (SNR). A spectral-analysis technique applicable to a DM encoded signal is developed to obtain SNR curves.

Locicero, J. L.↗
NASA NTRS1978

FPLA mechanization of arithmetic elements to produce A + B or to pass A only

A 4-bit and a 3-bit adder are described which can be implemented under special hardware restrictions. The chip to be used is field-programmable logic array (FPLA) with 12 input lines, 50 AND gates inside, and output through only 6 OR gates. The context in which it is being used requires an enable function which can suppress one of the two numbers to be added. The 3-bit enabled adder is compatible with lookahead-carry mechanizations using the 74S182.

Wallis, D. E.↗
NASA NTRS1986

Derivatives of the Arithmetic-Geometric Mean

Developed for theoretical studies of lightning requiring estimates of electric fields in clouds, the technique is expected to reduce computation time and improve accuracy.

Taton, F. B.↗
NASA NTRS1986

Workspace Program for Complex-Number Arithmetic

COMPLEX is workspace program designed to empower APL with complexnumber capabilities. Complex-variable methods provide analytical tools invaluable for applications in mathematics, science, and engineering. COMPLEX written in APL.

Patrick, M. C.↗
NASA NTRS1990

Application specific serial arithmetic arrays

High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed for specific applications by applying hardware description language techniques to a library of full-custom CMOS building blocks. Single clock pre-charged circuits have been implemented for these arrays at clock rates in excess of 100 Mhz using economical 2-micron (minimum feature size) CMOS processes, which may be quickly configured for a variety of applications. A number of application-specific arrays are presented, including a 2-D convolver for image processing, an integer polynomial solver, and a finite-field polynomial solver.

Winters, K.↗