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Professor Elbuluk will develop circuits for operation at extremely low temperatures down to -230 C. As a part of his work, he will evaluate (at low temperatures) devices to be used in the circuits.
New power control technologies, such as smart power (SP) and power integrated circuits (PICs), are being developed to decrease cost and increase performance of photovoltaic power arrays.
An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.
A quantum dot structure having a split-gate geometry is provided. The quantum dot is configured for incorporation into a quantum dot array of a quantum processing unit. A gap between a reservoir accumulation gate and a quantum dot accumulation gate provides a tunnel barrier between an electric charge reservoir and a quantum dot well. An electrical potential applied to the gates defines a tunnel barrier height, width and charge tunneling rate between the well and the reservoir without relying on any barrier gate to control the charge tunneling rate.
Electron microbeam testing of integrated circuits
Electronic developments in semiconductor circuits - Digital logic circuits
LSI circuits in space electronics, discussing packaging, reliability, applications, etc
Flexible circuits with superconducting wiring atop polyimide thin films are being studied to connect large numbers of wires between stages in cryogenic apparatus with low heat load. The feasibility of a full microstrip process, consisting of two layers of superconducting material separated by a thin dielectric layer on 5 mil (approximately 0.13 mm) Kapton sheets, where manageable residual stress remains in the polyimide film after processing, has been demonstrated. The goal is a 2-mil (approximately 0.051-mm) process using spin-on polyimide to take advantage of the smoother polyimide surface for achieving highquality metal films. Integration of microstrip wiring with this polyimide film may require high-temperature bakes to relax the stress in the polyimide film between metallization steps.
Technical aspects of using electronic logic circuits for automatic monitoring in space biology and medicine
The Mars In-Situ Propellant Production (ISPP) Precursor (MIP) experiment package is planned for inclusion on the Mars 2001 Lander. This experiment package consists of five experiments whose purpose is to demonstrate the performance of various ISPP processes in-situ on Mars. The demonstrated ability to produce propellant for Mars Return Vehicles (MRV) is considered to be a necessary precursor to any future manned mission to Mars. The Mars Thermal Environment/Radiator Characterization (MTERC) experiment is part of the MIP package and is intended to determine the Mars night sky temperature as well as to characterize the performance degradation of radiators caused by environmental exposure on Mars over time. Radiators are needed as part of the ISPP process to remove heat from the Mars Atmosphere Acquisition and Compression (MAAC) CO2 sorption compressor. MTERC will provide the data needed to optimize the design of radiators for ISPP and other processes. A MTERC Development Unit (DU) has been fabricated and tested at JPL. The MTERC DU consists of 1) a radiator subassembly, 2) a motor/cover subassembly, 3) a differential temperature control circuit and motor control electronics circuit board, and 4) a command and data handling electronics circuit board. This paper will describe the operational theory and the configuration of the MTERC DU and will discuss the current status of the MTERC experiment development including some selected results of performance testing that has been completed prior to the ISRU III meeting.
The Mars In-Situ Propellant Production (ISPP) Precursor (MIP) experiment package is planned for inclusion on the Mars 2001 Lander. This experiment package consists of five experiments whose purpose is to demonstrate the performance of various ISPP processes in-situ on Mars. The demonstrated ability to produce propellant for Mars Return Vehicles (MRV) is considered to be a necessary precursor to any future manned mission to Mars. The Mars Thermal Environment/Radiator Characterization (MTERC) experiment is part of the MIP package and is intended to determine the Mars night sky temperature as well as to characterize the performance degradation of radiators caused by environmental exposure on Mars over time. Radiators are needed as part of the ISPP process to remove heat from the Mars Atmosphere Acquisition and Compression (MAAC) C02 sorption compressor. MTERC will provide the data needed to optimize the design of radiators for ISPP and other processes. A MTERC Development Unit (DU) has been fabricated and tested at JPL. The MTERC DU consists of: (1) a radiator subassembly, (2) a motor/cover subassembly, (3) a differential temperature control circuit and motor control electronics circuit board, and (4) a command and data handling electronics circuit board. This paper will describe the operational theory and the configuration of the MTERC DU and will discuss the current status of the MTERC experiment development including some selected results of performance testing that has been completed prior to the ISRU III meeting.
A modular electronics packaging system includes multiple packaging slices that are mounted horizontally to a base structure. The slices interlock to provide added structural support. Each packaging slice includes a rigid and thermally conductive housing having four side walls that together form a cavity to house an electronic circuit. The chamber is enclosed on one end by an end wall, or web, that isolates the electronic circuit from a circuit in an adjacent packaging slice. The web also provides a thermal path between the electronic circuit and the base structure. Each slice also includes a mounting bracket that connects the packaging slice to the base structure. Four guide pins protrude from the slice into four corresponding receptacles in an adjacent slice. A locking element, such as a set screw, protrudes into each receptacle and interlocks with the corresponding guide pin. A conduit is formed in the slice to allow electrical connection to the electronic circuit.
Linear Variable Differential Transformer /LVDT/ electronic skewing circuit guides a long cylindrical capsule underwater into a larger tube so that it does not contact the tube wall. This device detects movement of the capsule from a reference point and provides a continuous signal that is monitored on an oscilloscope.
Intelligent electronic circuit is used to monitor other circuits within module and to warn of imminent failure of module under surveillance. Monitor is housed in rectangular connector and plugs into mating jack originally designed to terminate flat conductor cables. Device can be made from existing premolded rectangular connectors.
A compact electronic circuit was developed to detect prelasing in Q-swithed pulsed laser systems and once detected to shut down the laser before the next laser pulse occurs. The circuit is small, compact, and uses a minimum of components which makes it quite economical, thus readily lending itself to commercial applications. It can easily be incorporated into virtually any Q-switched laser system or reliability of a laser system by reducing a source of possible costly optical damage. The circuit operation and instrument requirements necessary to incorporate the circuit into a laser system are discussed.
Standard dosimeter reader, modified by adding an electronic gating circuit to trigger the intensity level photomultiplier, increases readout sensitivity of photoluminescent dosimeter systems. The gating circuit is controlled by a second photomultiplier which senses a short ultraviolet pulse from a laser used to excite the dosimeter.
Efforts are under way to apply the concept of evolvable hardware (EHW) to compensate for variations, with temperature, in the operational characteristics of electronic circuits. To maintain the required functionality of a given circuit at a temperature above or below the nominal operating temperature for which the circuit was originally designed, a new circuit would be evolved; moreover, to obtain the required functionality over a very wide temperature range, there would be evolved a number of circuits, each of which would satisfy the performance requirements over a small part of the total temperature range. The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles, namely, "Reconfigurable Arrays of Transistors for Evolvable Hardware" (NPO-20078), Vol. 25, No. 2 (February 2001), page 36; Evolutionary Automated Synthesis of Electronic Circuits (NPO- 20535), Vol. 26, No. 7 (July 2002), page 37; "Designing Reconfigurable Antennas Through Hardware Evolution" (NPO-20666), Vol. 26, No. 7 (July 2002), page 38; "Morphing in Evolutionary Synthesis of Electronic Circuits" (NPO-20837), Vol. 26, No. 8 (August 2002), page 31; "Mixtrinsic Evolutionary Synthesis of Electronic Circuits" (NPO-20773) Vol. 26, No. 8 (August 2002), page 32; and "Synthesis of Fuzzy-Logic Circuits in Evolvable Hardware" (NPO-21095) Vol. 26, No. 11 (November 2002), page 38. To recapitulate from the cited prior articles: EHW is characterized as evolutionary in a quasi-genetic sense. The essence of EHW is to construct and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The connection and disconnection can be effected by use of field-programmable transistor arrays (FPTAs). The evolution is guided by a search-andoptimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by mathematical modeling (that is, computational simulation) only, tested in real hardware, or tested in combinations of computational simulation and real hardware.
The Xyce Parallel Electronic Simulator simulates electronic circuit behavior in DC, AC, HB, MPDE and transient mode using standard analog (DAE) and/or device (PDE) device models including several age and radiation aware devices. It supports a variety of computing platforms (both serial and parallel) computers. Lastly, it uses a variety of modern solution algorithms dynamic parallel load-balancing and iterative solvers.! ! Xyce is primarily used to simulate the voltage and current behavior of a circuit network (a network of electronic devices connected via a conductive network). As a tool, it is mainly used for the design and analysis of electronic circuits.! ! Kirchoff's conservation laws are enforced over a network using modified nodal analysis. This results in a set of differential algebraic equations (DAEs). The resulting nonlinear problem is solved iteratively using a fully coupled Newton method, which in turn results in a linear system that is solved by either a standard sparse-direct solver or iteratively using Trilinos linear solver packages, also developed at Sandia National Laboratories.