Search NASA⌕ Search

SEARCH · Search NASA

Results for “FPGA”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 73 records · Page 4

FPGA-Accelerated Range-Limited Molecular Dynamics

Long timescale Molecular Dynamics (MD) simulation of small molecules is crucial in drug design and basic science. To accelerate a small data set that is executed for a large number of iterations, high-efficiency is required. Recent work in this domain has demonstrated that among COTS devices only FPGA-centric clusters can scale beyond a few processors. The problem addressed here is that, as the number of on-chip processors has increased from fewer than 10 into the hundreds, previous intra-chip routing solutions are no longer viable. We find, however, that through various design innovations, high efficiency can be maintained. These include replacing the previous broadcast networks with ring-routing and then augmenting the rings with out-of-order and caching mechanisms. Others are adding a level of hierarchical filtering and memory recycling. Two novel optimized architectures emerge, together with a number of variations. These are validated, analyzed, and evaluated. We find that in the domain of interest speed-ups over GPUs are achieved. Finally, the potential impact is that this system promises to be the basis for scalable long timescale MD with commodity clusters.

97 MATHEMATICS AND COMPUTING↗

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

97 MATHEMATICS AND COMPUTING↗

FPGA-based tracking for the CMS Level-1 trigger using the tracklet algorithm

The high instantaneous luminosities expected following the upgrade of the Large Hadron Collider (LHC) to the High-Luminosity LHC (HL-LHC) pose major experimental challenges for the CMS experiment. A central component to allow efficient operation under these conditions is the reconstruction of charged particle trajectories and their inclusion in the hardware based trigger system. There are many challenges involved in achieving this: a large input data rate of about 20–40 Tb/s; processing a new batch of input data every 25 ns, each consisting of about 15,000 precise position measurements and rough transverse momentum measurements of particles (“stubs”); performing the pattern recognition on these stubs to find the trajectories; and producing the list of trajectory parameters within 4 µs. Here, this paper describes a proposed solution to this problem, specifically, it presents a novel approach to pattern recognition and charged particle trajectory reconstruction using an all-FPGA solution. The results of an end-to-end demonstrator system, based on Xilinx Virtex-7 FPGAs, that meets timing and performance requirements are presented along with a further improved, optimized version of the algorithm together with its corresponding expected performance.

47 OTHER INSTRUMENTATION↗

High performance FPGA embedded system for machine learning based tracking and trigger in sPhenix and EIC

We present a comprehensive end-to-end pipeline to classify triggers versus background events in this paper. This pipeline makes online decisions to select signal data and enables the intelligent trigger system for efficient data collection in the Data Acquisition System (DAQ) of the upcoming sPHENIX and future EIC (Electron-Ion Collider) experiments. Starting from the coordinates of pixel hits that are lightened by passing particles in the detector, the pipeline applies three-stage of event processing (hits clustering, track reconstruction, and trigger detection) and labels all processed events with the binary tag of trigger versus background events. The pipeline consists of deterministic algorithms such as clustering pixels to reduce event size, tracking reconstruction to predict candidate edges, and advanced graph neural network-based models for recognizing the entire jet pattern. In particular, we apply the message-passing graph neural network to predict links between hits and reconstruct tracks and a hierarchical pooling algorithm (DiffPool) to make the graph-level trigger detection. We obtain an impressive performance (≥70% accuracy) for trigger detection with only 3200 neuron weights in the end-to-end pipeline. We deploy the end-to-end pipeline into a field-programmable gate array (FPGA) and accelerate the three stages with speedup factors of 1152, 280, and 21, respectively.

Instruments & Instrumentation↗

Embedded FPGA developments in 130 nm and 28 nm CMOS for machine learning in particle detector readout

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Finally, further development of the eFPGA technology and its application to collider detector readout is discussed.

47 OTHER INSTRUMENTATION↗

A Framework for Neural Network Inference on FPGA-Centric SmartNICs

FPGA-based SmartNICs offer great potential to significantly improve the performance of high-performance computing and warehouse data processing by tightly coupling support for reconfigurable data-intensive computation with cross-node communication, thereby mitigating the von Neumann bottleneck. Existing work, however, has been generally been limited in that it assumes an accelerator model where kernels are offloaded to SmartNICs, but most control tasks are left to the CPUs. This leads to frequent waiting, inferior performance, and scaling challenges. In this work, we propose a new distributive data-centric computing framework, named FCsN, for reconfigurable SmartNIC-based systems. Through a lightweight task circulation execution model and its implementation architecture, FCsN allows the complete detaching of kernel execution, control logic, system scheduling, and network communication to the SmarNICs. This boosts performance by: (i) avoiding the control dependency with CPUs and (ii) supporting streaming kernel execution and network communication at line rate and in a very fine-grained manner. We demonstrate the efficiency and flexibility of FCsN using various types of neural network applications including graph neural networks; as these last are both irregular and data intensive they offer an especially robust demonstration. Evaluations using commonly-used neural network models and graph datasets show that a system with the support of FCsN can achieve, on average, 144 speedups over the MPI-based standard CPU baselines.

Guo, Anqi↗

FPGA Computing

The articles in this special section focus on cutting-edge research on topics that relate to field programmable gate arrays (FPGA) in computing.

97 MATHEMATICS AND COMPUTING↗

A Length Adaptive Algorithm-Hardware Co-design of Transformer on FPGA Through Sparse Attention and Dynamic Pipelining

Transformers are considered one of the most important deep learning models since 2018, in part because it establishes state-of-the-art (SOTA) records and could potentially replace existing Deep Neural Networks (DNNs). Despite the remarkable triumphs, the prolonged turnaround time of Transformer models is a widely recognized roadblock. The variety of sequence lengths imposes additional computing overhead where inputs need to be zero-padded to the maximum sentence length in the batch to accommodate the parallel computing platforms. This paper targets the field-programmable gate array (FPGA) and proposes a coherent sequence length adaptive algorithm–hardware co-design for Transformer acceleration. Particularly, we develop a hardware-friendly sparse attention operator and a length-aware hardware resource scheduling algorithm. The proposed sparse attention operator brings the complexity of attention-based models down to linear complexity and alleviates the off-chip memory traffic. The proposed length-aware resource hardware scheduling algorithm dynamically allocates the hardware resources to fill up the pipeline slots and eliminates bubbles for NLP tasks. Experiments show that our design has very small accuracy loss and has 80.2 × and 2.6 × speedup compared to CPU and GPU implementation, and 4 × higher energy efficiency than state-of-the-art GPU accelerator optimized via CUBLAS GEMM.

Peng, Hongwu↗

ESnet-JLab FPGA Accelerated Transport (control plane) [EJFAT (udplbd2)] v2.0

The ESnet-JLab FPGA Accelerated Transport system is a solution for streaming high-speed scientific measurement data from Data Acquisition Systems (DAQs) to high-performance computing facilties. It is generally compatible with many science workflows, and makes no assumptions about the specifics of any particular experiment. This program (udplbd version 2) implements the control plane for the system. It is responsible for programming network forwarding rules into the data plane (implemented by the hardware designed named udplb, described separately). It also implements the control loop necessary to match up offered workload with available capacity on high-performance compute nodes.

Howard, Derek [Lawrence Berkeley National Laborato↗

Extinction Monitoring of Pulsed Proton Beams Using FPGA-Based Peak Detection

The Mu2e experiment at Fermilab imposes stringent requirements on the elimination of out-of-time beam in its pulsed proton beam - a requirement known as "extinction". We present a method to measure the out-of-time particle rates to calculate the level of extinction in the inter-pulse gaps. The proposed method utilizes an array of quartz Cherenkov radiators and photomultiplier tubes to detect particles scattered from a vacuum chamber in the M4 transfer beamline at Fermilab.The measurement will employ a new μTCA-based FPGA system for data acquisition and signal processing, utilizing real-time peak detection algorithms to count scattered beam particles. By integrating data over many transfers, the time profile of the out-of-time beam will be resolved to fractional levels relative to that of the in-time beam. These results are compared with G4beamline simulations to validate models of beam transport, dynamics, and extinction, providing critical input for optimizing beam delivery to Mu2e.

Hensley, Ryan [UC, Davis]↗

Calculating beam extinction in a pulsed proton beam using FPGA-based peak detection

The Mu2e experiment at Fermilab imposes stringent requirements on the elimination of out-of-time beam in its pulsed proton beam, a requirement known as “extinction”. Utilizing a new μTCA-based FPGA data acquisition system, we recorded live particle data from scattered particles incident on an array of quartz Cherenkov radiators and photomultiplier tubes to measure the extinction in the inter-pulse gaps in the pulsed proton beam. Minuscule errors in the derived signal period can make a measurement of the extinction impossible, so after taking a Fourier transform, further optimizations on the period were done based on the assumption that the signal period is stable over the full time of the beam spill while it is being resonantly extracted. After these optimizations, the beam extinction was shown to be on the level of 10^3.

Hensley, Ryan [UC, Davis]↗

FPGA-Based Spill Regulation System for the Muon Delivery Ring at Fermilab

The Muon to Electron Experiment (Mu2e) requires a uniform beam profile from the Muon Delivery Ring to meet their experimental needs. A specialized Spill Regulation System (SRS) has been developed to help achieve consistent spill uniformity. The system is based on a custom-designed carrier board featuring an Arria 10 SoC, capable of executing real-time feedback control. The FPGA processes beam pulses of approximately 200 ns every 1.695 $μ$s, allowing for continuous monitoring of the extracted spill intensity through fast bunch integration. The system directly controls three quadrupole magnets, which work in conjunction with sextupole magnets to achieve third-order resonant extraction. Furthermore, the board interfaces with Fermilab's Accelerator Control Network (ACNET), enabling operators to modify spill regulation settings in real-time via the control network while providing diagnostic waveforms. These waveforms help operators monitor the process and fine-tune the feedback mechanisms. This paper presents an overview of the board's architecture and its initial progress toward regulating beam extraction. This initial version of the regulation system aims to evaluate baseline performance to inform future system improvements.

Berlioz, J. R. [Fermilab]↗

Improving Signal-to-Noise Ratio (SNR) for Quantum Readout Signals Using Adaptive Hardware Filters on FPGA

This research presents an innovative approach to improving the Signal-to-Noise Ratio (SNR) in superconducting quantum computing readout signals, utilizing FPGA-based adaptive filtering on the control board. Our solution aims to bolster quantum computations' reliability by providing a more accurate and precise way to obtain our readout traces and achieve a higher discernability between excitation states in real-time.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

A self-certifying FPGA based pixel readout chip test system for CMS ETL upgrade

A flexible self-certifying pixel readout test system for testing the Endcap Timing Read-Out Chip (ETROC) has been developed for the CMS MIP Timing Detector (MTD), part of the upgrade for the HL-LHC. The system includes an FPGA-based (Xilinx KC705) test system that can take data from an emulator or up to four ETROC boards in telescope mode. A python based DAQ system simplifies configuration, calibration, and testing of the chips. The system provides an efficient & reliable solution for testing ETROC (ETROC2 since April 2023 with 16x16 pixels, full-size, full functionality prototype) and can be extended to other readout chips with similar architecture (AIDA integration is currently being explored).

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

Lightweight Embedded Controller in Advanced FPGA SoC for Radar Signal Processing [Poster]

The objective of the project is to demonstrate that critical control functions can be implemented using little resources in modern microelectronics. A finite state machine (Figure 1) is implemented onto a field programmable gate array (FPGA). The functionality of the system is demonstrated by sending binary instructions to the controller. The controller transmits patterns through an LED, controls an electromechanical device, and uses pulse-width modulation (PWM) for radar functions.

42 ENGINEERING↗

An Arbitrary Time Interval Generator Base on Vernier Clocks with 0.67 ps Adjustable Steps Implemented in FPGA

In TDC testing or timing system implementation tasks, it is often desirable to generate signal pulses with fine adjustable time intervals. In delay cell-based schemes, the time adjustment steps are limited by the propagation delays of the cells, which are typically 15 to 20 picoseconds per step and are sensitive to temperature and operating voltage. In this document, a purely digital scheme based on two vernier clocks with small frequency difference generated using cascaded PLL is reported. The scheme is tested in two families of low-cost FPGA and 0.67 and 0.97 picoseconds adjustable steps of the time intervals are achieved.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

FPGA-Based Spill Regulation System for the Muon Delivery Ring at Fermilab

The Muon to Electron Experiment (\acrshort{Mu2e}) requires a uniform beam profile from the Muon Delivery Ring to meet their experimental needs. A specialized Spill Regulation System (\acrshort{SRS}) has been developed to help achieve consistent spill uniformity. The system is based on a custom-designed carrier board featuring an Arria 10 SoC, capable of executing real-time feedback control. The FPGA processes beam pulses of approximately 200 ns every 1.695 microseconds, allowing for continuous monitoring of the extracted spill intensity through fast bunch integration. The system directly controls three quadrupole magnets, which work in conjunction with sextupole magnets to achieve third-order resonant extraction. Furthermore, the board interfaces with Fermilab s Accelerator Control Network (ACNET), enabling operators to modify spill regulation settings in real-time via the control network while providing diagnostic waveforms. These waveforms help operators monitor the process and fine-tune the feedback mechanisms. This paper presents an overview of the board's architecture and its initial progress toward regulating beam extraction. This initial version of the regulation system aims to evaluate baseline performance to inform future system improvements.

Berlioz, Jose Rene [Fermilab]↗

A 3D FPGA Track Segment Seeding Engine Based on the Tiny Triplet Finder

A 3D track segment seeding engine core based on the Tiny Triplet Finder has been implemented and tested in a low-cost FPGA device. The seeding engine is designed to preselect and group hits (stubs) from cylindrical detector layers to feed subsequent track fitting stage. The seeding engine consists of a Hough transform space for r-z view and a Tiny Triplet Finder for r-phi view to implement 3D constraints. The seeding engine is organized as a pipeline so that each hit is processed in a single clock cycle. Test results show that the seeding engine operates as expected.

Wu, Jinyuan↗