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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS2014

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Xilinx FPGA↗
NASA NTRS1971

Integrated thin film cadmium sulfide solar cell module

The design, development, fabrication and tests of flexible integrated thin-film cadmium sulfide solar cells and modules are discussed. The development of low cost and high production rate methods for interconnecting cells into large solar arrays is described. Chromium thin films were applied extensively in the deposited cell structures as a means to: (1) achieve high adherence between the cadmium sulfide films and the vacuum-metallized copper substrates, (2) obtain an ohmic contact to the cadmium sulfide films, and (3) improve the adherence of gold films as grids or contact areas.

Mickelsen, R. A.↗
NASA NTRS1990

Mapping unstructured grid problems to the connection machine

We present a highly parallel graph mapping technique that enables one to solve unstructured grid problems on massively parallel computers. Many implicit and explicit methods for solving discretizated partial differential equations require each point in the discretization to exchange data with its neighboring points every time step or iteration. The time spent communicating can limit the high performance promised by massively parallel computing. To eliminate this bottleneck, we map the graph of the irregular problem to the graph representing the interconnection topology of the computer such that the sum of the distances that the messages travel is minimized. We show that, in comparison to a naive assignment of processors, our heuristic mapping algorithm significantly reduces the communication time on the Connection Machine, CM-2.

Hammond, Steven W.↗
NASA NTRS1990

Solving unstructured grid problems on massively parallel computers

A highly parallel graph mapping technique that enables one to efficiently solve unstructured grid problems on massively parallel computers is presented. Many implicit and explicit methods for solving discretized partial differential equations require each point in the discretization to exchange data with its neighboring points every time step or iteration. The cost of this communication can negate the high performance promised by massively parallel computing. To eliminate this bottleneck, the graph of the irregular problem is mapped into the graph representing the interconnection topology of the computer such that the sum of the distances that the messages travel is minimized. It is shown that using the heuristic mapping algorithm significantly reduces the communication time compared to a naive assignment of processes to processors.

Hammond, Steven W.↗
NASA NTRS2005

High Resolution Aerospace Applications using the NASA Columbia Supercomputer

This paper focuses on the parallel performance of two high-performance aerodynamic simulation packages on the newly installed NASA Columbia supercomputer. These packages include both a high-fidelity, unstructured, Reynolds-averaged Navier-Stokes solver, and a fully-automated inviscid flow package for cut-cell Cartesian grids. The complementary combination of these two simulation codes enables high-fidelity characterization of aerospace vehicle design performance over the entire flight envelope through extensive parametric analysis and detailed simulation of critical regions of the flight envelope. Both packages. are industrial-level codes designed for complex geometry and incorpor.ats. CuStomized multigrid solution algorithms. The performance of these codes on Columbia is examined using both MPI and OpenMP and using both the NUMAlink and InfiniBand interconnect fabrics. Numerical results demonstrate good scalability on up to 2016 CPUs using the NUMAIink4 interconnect, with measured computational rates in the vicinity of 3 TFLOP/s, while InfiniBand showed some performance degradation at high CPU counts, particularly with multigrid. Nonetheless, the results are encouraging enough to indicate that larger test cases using combined MPI/OpenMP communication should scale well on even more processors.

Mavriplis, Dimitri J.↗
NASA NTRS2001

A Parallel Multigrid Solver for Viscous Flows on Anisotropic Structured Grids

This paper presents an efficient parallel multigrid solver for speeding up the computation of a 3-D model that treats the flow of a viscous fluid over a flat plate. The main interest of this simulation lies in exhibiting some basic difficulties that prevent optimal multigrid efficiencies from being achieved. As the computing platform, we have used Coral, a Beowulf-class system based on Intel Pentium processors and equipped with GigaNet cLAN and switched Fast Ethernet networks. Our study not only examines the scalability of the solver but also includes a performance evaluation of Coral where the investigated solver has been used to compare several of its design choices, namely, the interconnection network (GigaNet versus switched Fast-Ethernet) and the node configuration (dual nodes versus single nodes). As a reference, the performance results have been compared with those obtained with the NAS-MG benchmark.

Prieto, Manuel↗
NASA NTRS2005

Navier-Stokes Simulation of Airconditioning Facility of a Large Modem Computer Room

NASA recently assembled one of the world's fastest operational supercomputers to meet the agency's new high performance computing needs. This large-scale system, named Columbia, consists of 20 interconnected SGI Altix 512-processor systems, for a total of 10,240 Intel Itanium-2 processors. High-fidelity CFD simulations were performed for the NASA Advanced Supercomputing (NAS) computer room at Ames Research Center. The purpose of the simulations was to assess the adequacy of the existing air handling and conditioning system and make recommendations for changes in the design of the system if needed. The simulations were performed with NASA's OVERFLOW-2 CFD code which utilizes overset structured grids. A new set of boundary conditions were developed and added to the flow solver for modeling the roomls air-conditioning and proper cooling of the equipment. Boundary condition parameters for the flow solver are based on cooler CFM (flow rate) ratings and some reasonable assumptions of flow and heat transfer data for the floor and central processing units (CPU) . The geometry modeling from blue prints and grid generation were handled by the NASA Ames software package Chimera Grid Tools (CGT). This geometric model was developed as a CGT-scripted template, which can be easily modified to accommodate any changes in shape and size of the room, locations and dimensions of the CPU racks, disk racks, coolers, power distribution units, and mass-storage system. The compute nodes are grouped in pairs of racks with an aisle in the middle. High-speed connection cables connect the racks with overhead cable trays. The cool air from the cooling units is pumped into the computer room from a sub-floor through perforated floor tiles. The CPU cooling fans draw cool air from the floor tiles, which run along the outside length of each rack, and eject warm air into the center isle between the racks. This warm air is eventually drawn into the cooling units located near the walls of the room. One major concern is that the hot air ejected to the middle isle might recirculate back into the cool rack side and cause thermal short-cycling. The simulations analyzed and addressed the following important elements of the computer room: 1) High-temperature build-up in certain regions of the room; 2) Areas of low air circulation in the room; 3) Potential short-cycling of the computer rack cooling system; 4) Effectiveness of the perforated cooling floor tiles; 5) Effect of changes in various aspects of the cooling units. Detailed flow visualization is performed to show temperature distribution, air-flow streamlines and velocities in the computer room.

Source record↗
NASA NTRS2001

Latency Hiding in Dynamic Partitioning and Load Balancing of Grid Computing Applications

The Information Power Grid (IPG) concept developed by NASA is aimed to provide a metacomputing platform for large-scale distributed computations, by hiding the intricacies of highly heterogeneous environment and yet maintaining adequate security. In this paper, we propose a latency-tolerant partitioning scheme that dynamically balances processor workloads on the.IPG, and minimizes data movement and runtime communication. By simulating an unsteady adaptive mesh application on a wide area network, we study the performance of our load balancer under the Globus environment. The number of IPG nodes, the number of processors per node, and the interconnected speeds are parameterized to derive conditions under which the IPG would be suitable for parallel distributed processing of such applications. Experimental results demonstrate that effective solution are achieved when the IPG nodes are connected by a high-speed asynchronous interconnection network.

Das, Sajal K.↗
NASA NTRS2013

NASA Tech Briefs, May 2013

Topics include: Test Waveform Applications for JPL STRS Operating Environment; Pneumatic Proboscis Heat-Flow Probe; Method to Measure Total Noise Temperature of a Wireless Receiver During Operation; Cursor Control Device Test Battery; Functional Near-Infrared Spectroscopy Signals Measure Neuronal Activity in the Cortex; ESD Test Apparatus for Soldering Irons; FPGA-Based X-Ray Detection and Measurement for an X-Ray Polarimeter; Sequential Probability Ratio Test for Spacecraft Collision Avoidance Maneuver Decisions; Silicon/Carbon Nanotube Photocathode for Splitting Water; Advanced Materials and Fabrication Techniques for the Orion Attitude Control Motor; Flight Hardware Packaging Design for Stringent EMC Radiated Emission Requirements; RF Reference Switch for Spaceflight Radiometer Calibration; An Offload NIC for NASA, NLR, and Grid Computing; Multi-Scale CNT-Based Reinforcing Polymer Matrix Composites for Lightweight Structures; Ceramic Adhesive and Methods for On-Orbit Repair of Re-Entry Vehicles; Self-Healing Nanocomposites for Reusable Composite Cryotanks; Pt-Ni and Pt-Co Catalyst Synthesis Route for Fuel Cell Applications; Aerogel-Based Multilayer Insulation with Micrometeoroid Protection; Manufacturing of Nanocomposite Carbon Fibers and Composite Cylinders; Optimized Radiator Geometries for Hot Lunar Thermal Environments; A Mission Concept: Re-Entry Hopper-Aero-Space-Craft System on-Mars (REARM-Mars); New Class of Flow Batteries for Terrestrial and Aerospace Energy Storage Applications; Reliability of CCGA 1152 and CCGA 1272 Interconnect Packages for Extreme Thermal Environments; Using a Blender to Assess the Microbial Density of Encapsulated Organisms; Mixed Integer Programming and Heuristic Scheduling for Space Communication; Video Altimeter and Obstruction Detector for an Aircraft; Control Software for Piezo Stepping Actuators; Galactic Cosmic Ray Event-Based Risk Model (GERM) Code; Sasquatch Footprint Tool; and Multi-User Space Link Extension (SLE) System.

Source record↗
NASA NTRS2010

The Assurance Challenges of Advanced Packaging Technologies for Electronics

Advances in microelectronic parts performance are driving towards finer feature sizes, three-dimensional geometries and ever-increasing number of transistor equivalents that are resulting in increased die sizes and interconnection (I/O) counts. The resultant packaging necessary to provide assemble-ability, environmental protection, testability and interconnection to the circuit board for the active die creates major challenges, particularly for space applications, Traditionally, NASA has used hermetically packaged microcircuits whenever available but the new demands make hermetic packaging less and less practical at the same time as more and more expensive, Some part types of great interest to NASA designers are currently only available in non-hermetic packaging. It is a far more complex quality and reliability assurance challenge to gain confidence in the long-term survivability and effectiveness of nonhermetic packages than for hermetic ones. Although they may provide more rugged environmental protection than the familiar Plastic Encapsulated Microcircuits (PEMs), the non-hermetic Ceramic Column Grid Array (CCGA) packages that are the focus of this presentation present a unique combination of challenges to assessing their suitability for spaceflight use. The presentation will discuss the bases for these challenges, some examples of the techniques proposed to mitigate them and a proposed approach to a US MIL specification Class for non-hermetic microcircuits suitable for space application, Class Y, to be incorporated into M. IL-PRF-38535. It has recently emerged that some major packaging suppliers are offering hermetic area array packages that may offer alternatives to the nonhermetic CCGA styles but have also got their own inspectability and testability issues which will be briefly discussed in the presentation,

Sampson, Michael J.↗
NASA NTRS2014

AE (Acoustic Emission) for Flip-Chip CGA/FCBGA Defect Detection

C-mode scanning acoustic microscopy (C-SAM) is a nondestructive inspection technique that uses ultrasound to show the internal feature of a specimen. A very high or ultra-high-frequency ultrasound passes through a specimen to produce a visible acoustic microimage (AMI) of its inner features. As ultrasound travels into a specimen, the wave is absorbed, scattered or reflected. The response is highly sensitive to the elastic properties of the materials and is especially sensitive to air gaps. This specific characteristic makes AMI the preferred method for finding "air gaps" such as delamination, cracks, voids, and porosity. C-SAM analysis, which is a type of AMI, was widely used in the past for evaluation of plastic microelectronic circuits, especially for detecting delamination of direct die bonding. With the introduction of the flip-chip die attachment in a package; its use has been expanded to nondestructive characterization of the flip-chip solder bumps and underfill. Figure 1.1 compares visual and C-SAM inspection approaches for defect detection, especially for solder joint interconnections and hidden defects. C-SAM is specifically useful for package features like internal cracks and delamination. C-SAM not only allows for the visualization of the interior features, it has the ability to produce images on layer-by-layer basis. Visual inspection; however, is only superior to C-SAM for the exposed features including solder dewetting, microcracks, and contamination. Ideally, a combination of various inspection techniques - visual, optical and SEM microscopy, C-SAM, and X-ray - need to be performed in order to assure quality at part, package, and system levels. This reports presents evaluations performed on various advanced packages/assemblies, especially the flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. Both external and internal equipment was used for evaluation. The outside facility provided images of the key features that could be detected using the most advanced C-SAM equipment with a skilled operator. Investigation continued using in-house equipment with its limitations. For comparison, representative X-rays of the assemblies were also gathered to show key defect detection features of these non-destructive techniques. Key images gathered and compared are: Compared the images of 2D X-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case, X-ray was a clear winner. Evaluated flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Only the FCCGA package that had no heat sink could be fully analyzed for underfill and bump quality. Cross-sectional microscopy did not revealed peripheral delamination features detected by C-SAM. Analyzed a number of fine pitch PBGA assemblies by C-SAM. Even though the internal features of the package assemblies could be detected, C-SAM was unable to detect solder joint failure at either the package or board level. Twenty times touch ups by solder iron with 700degF tip temperature, each with about 5 second duration, did not induce defects to be detected by C-SAM images. Other techniques need to be considered to induce known defects for characterization. Given NASA's emphasis on the use of microelectronic packages and assemblies and quality assurance on workmanship defect detection, understanding key features of various inspection systems that detect defects in the early stages of package and assembly is critical to developing approaches that will minimize future failures. Additional specific, tailored non-destructive inspection approaches could enable low-risk insertion of these advanced electronic packages having hidden and fine features.

Ghaffarian, Reza↗
NASA NTRS2001

A Latency-Tolerant Partitioner for Distributed Computing on the Information Power Grid

NASA's Information Power Grid (IPG) is an infrastructure designed to harness the power of graphically distributed computers, databases, and human expertise, in order to solve large-scale realistic computational problems. This type of a meta-computing environment is necessary to present a unified virtual machine to application developers that hides the intricacies of a highly heterogeneous environment and yet maintains adequate security. In this paper, we present a novel partitioning scheme. called MinEX, that dynamically balances processor workloads while minimizing data movement and runtime communication, for applications that are executed in a parallel distributed fashion on the IPG. We also analyze the conditions that are required for the IPG to be an effective tool for such distributed computations. Our results show that MinEX is a viable load balancer provided the nodes of the IPG are connected by a high-speed asynchronous interconnection network.

Das, Sajal K.↗
NASA NTRS2011

Reliability of Sn/Pb and Lead-Free (SnAgCu) Solders of Surface Mounted Miniaturized Passive Components for Extreme Temperature (-185 C to +125 C) Space Missions

Surface mount electronic package test boards have been assembled using tin/lead (Sn/Pb) and lead-free (Pb-free or SnAgCu or SAC305) solders. The soldered surface mount packages include ball grid arrays (BGA), flat packs, various sizes of passive chip components, etc. They have been optically inspected after assembly and subsequently subjected to extreme temperature thermal cycling to assess their reliability or future deep space, long-term, extreme temperature environmental missions. In this study, the employed temperature range (-185oC to +125oC) covers military specifications (-55oC to +100oC), extreme old Martian (-120oC to +115oC), asteroid Nereus (-180oC to +25oC) and JUNO (-150oC to +120oC) environments. The boards were inspected at room temperature and at various intervals as a function of extreme temperature thermal cycling and bake duration. Electrical resistance measurements made at room temperature are reported and the tests to date have shown some change in resistance as a function of extreme temperature thermal cycling and some showed increase in resistance. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work will be carried out to understand the reliability of packages under extreme temperature applications (-185oC to +125oC) via continuously monitoring the daisy chain resistance for BGA, Flat-packs, lead less chip packages, etc. This paper will describe the experimental reliability results of miniaturized passive components (01005, 0201, 0402, 0603, 0805, and 1206) assembled using surface mounting processes with tin-lead and lead-free solder alloys under extreme temperature environments.

extreme temperatures,↗
NASA NTRS2011

BOK-Underfill Optimization for FPGA Package/Assembly

Commercial-off-the-shelf area array package technologies in high-reliability versions are being considered for NASA electronic systems. These packages are prone to early failure due to the severe mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of ball interconnections decrease, susceptibility to mechanical loading and cycling fatigue grows. This report presents a summary of the body of knowledge developed for the evaluation of area array packages and is based on surveys of literature from industry and academia. For high-reliability applications, the limited data that exists will be presented. Most data from industry deals with mechanical fatigue caused by four-point bend tests, as well as from drop tests for hand-held electronics; the most recent data will be presented, along with a brief background of prior literature. Understanding the key design guidelines and failure mechanisms from past tests is critical to developing an approach that will minimize future failures. Additional specific testing enables low-risk insertion of these advanced electronic packages.

mechanical fatigue↗
NASA NTRS2007

Radiation Test Results for a MEMS Microshutter Operating at 60 K

The James Webb Space Telescope (JWST), the successor to the Hubble Space Telescope, is due to be launched in 2013 with the goal of searching the very distant Universe for stars that formed shortly after the Big Bang. Because this occurred so far back in time, the available light is strongly red-shifted, requiring the use of detectors sensitive to the infrared portion of the electromagnetic spectrum. HgCdTe infrared focal plane arrays, cooled to below 30 K to minimize noise, will be used to detect the faint signals. One of the instruments on JWST is the Near Infrared Spectrometer (NIRSPEC) designed to measure the infrared spectra of up to 100 separate galaxies simultaneously. A key component in NIRSPEC is a Micro-Electromechanical System (MEMS), a two-dimensional micro-shutter array (MSA) developed by NASA/GSFC. The MSA is inserted in front of the detector to allow only the light from the galaxies of interest to reach the detector and to block the light from all other sources. The MSA will have to operate at 30 K to minimize the amount of thermal radiation emitted by the optical components from reaching the detector array. It will also have to operate in the space radiation environment that is dominated by the MSA will be exposed to a large total ionizing dose of approximately 200 krad(Si). Following exposure to ionizing radiation, a variety of MEMS have exhibited performance degradation. MEMS contain moving parts that are either controlled or sensed by changes in electric fields. Radiation degradation can be expected for those devices where there is an electric field applied across an insulating layer that is part of the sensing or controlling structure. Ionizing radiation will liberate charge (electrons and holes) in the insulating layers, some of which may be trapped within the insulating layer. Trapped charge will partially cancel the externally applied electric field and lead to changes in the operation of the MEMS. This appears to be a general principle for MEMS. Knowledge of the above principle has raised the concern at NASA that the MSA might also exhibit degraded performance because, i) each shutter flap is a multilayer structure consisting of metallic and insulating layers and ii) the movement of the shutter flaps is partially controlled by the application of an electric field between the shutter flap and the substrate (vertical support grid). The whole mission would be compromised if radiation exposure were to prevent the shutters from opening and closing properly. energetic ionizing particles. Because it is located A unique feature of the MSA is that, as outside the spacecraft and has very little shielding, previously mentioned, it will have to operate at temperatures near 30 K. To date, there are no published reports on how very low temperatures (- 30K) affect the response of MEMS devices to total ionizing dose. Experiments on SiO2 structures at low temperatures (80 K) indicate that the electrons generated by the ionizing radiation are mobile and will move rapidly under the application of an external electric field. Holes, on the other hand, that would normally move in the opposite direction through the SiO2 via a "thermal hopping" process, are effectively immobile at low electric fields as they are trapped close to their generation sites. However, for sufficiently large electric fields (greater than 3 MV/cm) holes are able to move through the SiO2. The larger the field, the more rapidly the holes move. The separation of the electrons and holes leads to a reduced electric field within the insulating layer. To overcome this reduction in electric field, a greater external voltage will have to be applied that alters the normal operation of the device. This report presents the results of radiation testing of the MSA at 60 K. The temperature was higher than the targeted temperature because of a faulty electrical interconnect on the test board. Specifically, our goal was to determine whether the MSA would function propey after a TID of 200 krad(Si).

Rapchun, David A.↗