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57 records · Page 4

Direct pulse-level compilation of arbitrary quantum logic gates on superconducting qutrits

Advanced simulations and calculations on quantum computers require high-fidelity implementations of quantum operations. The universal gateset approach builds complex unitaries from a small set of primitive gates, often resulting in a long gate sequence, which is typically a leading factor in the total accumulated error. Compiling a complex unitary for processors with higher-dimensional logical elements, such as qutrits, exacerbates the accumulated error per unitary, since an even longer gate sequence is required. Optimal control methods promise time- and resource-efficient compact gate sequences and, therefore, higher fidelity. These methods generate pulses that can directly implement any complex unitary on a quantum device. In this work, we demonstrate that any arbitrary qubit and qutrit gate can be realized with high fidelity, which can significantly reduce the length of a gate sequence. We generate and test pulses for a large set of randomly selected arbitrary unitaries on several quantum processing units (QPUs): the Lawrence Livermore National Laboratory Quantum Device and Integration Testbed’s (QuDIT’s) standard QPU and three of Rigetti’s QPUs: Ankaa-2, Ankaa-9Q-1, and Aspen-M-3. On the QuDIT platform’s standard QPU, the average fidelity of random qutrit gates is 97.9 ± 0.5% measured with conventional QPT and 98.8 ± 0.6% from QPT with gate folding. Rigetti’s Ankaa-2 achieves random qubit gates with an average fidelity of 98.4 ± 0.5% (conventional QPT) and 99.7 ± 0.1% (QPT with gate folding). On Ankaa-9Q-1 and Aspen-M-3, the average fidelities with conventional qubit QPT measurements were higher than 99% (see Appendix). Here we show that optimal control gates are robust to drift for at least 3 h and that the same calibration parameters can be used for all implemented gates. Our work promises that the calibration overheads for optimal control gates can be made small enough to enable efficient quantum circuits based on this technique.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Synthesis of Correct Digital Controller Models from Specifications by Model Transformation (21-0320)

The design of high consequence controllers (in weapons systems, autonomy, etc.) that do what they are supposed to do is a significant challenge. Testing simply does not come close to meeting the requirements for assurance. Today circuit designers at Sandia (and elsewhere) typically capture the core behavior of their components using state models in tools such as STATEFLOW. They then check that their models meet certain requirements (e.g. “The system bus must not deadlock” or “both traffic lights at an intersection must not be green at the same time”) using tools called model checkers. If the model checker returns “yes” then the property is guaranteed to be satisfied by the model. However, there are several drawbacks to this industry practice: (1) there is a lot of detail to get right, this is particularly challenging when there are multiple components requiring complex coordination (2) any errors returned by the model checker have to be traced back through the design and fixed, necessitating rework, (3) there are severe scalability problems with this approach, particularly when dealing with concurrency. All this places high demands on the designers who now face not only an accelerated schedule but also controllers of increasing complexity. This report describes a new and fundamentally different approach to the construction of safety-critical digital controllers. Instead of directly constructing a complete model and then trying to verify it, the designer can start with an initial abstract (think “sketch”) model plus the requirements, from which a correct concrete model is automatically synthesized. There is no need for post-hoc verification of required functional properties. Having tool to carry this out will significantly impact the nation’s ability to ensure the safety of high-consequence digital systems. The approach has been implemented in a prototype tool, along with a suite of examples, including ones that reflect actual problems faced by designers. Our approach operates on a variant of Statecharts developed at Sandia called Qspecs. Statecharts are a widely used formalism for developing concurrent reactive systems, supporting scalability through allowing state models containing composite states, which are the serial or parallel composition of substates which can themselves contain statecharts. Statecharts enable an incremental style of development, in which states are progressively refined to incorporate greater detail in an incremental model of software development. Our approach formulates a set of constraints from the structure of the models and the requirements and propagates these constraints to a fixpoint. The solution to the constraints is an inductive invariant along with guards on the transitions. We also show how our approach extends to implementation refinement, decomposition, composition, and elaboration. We currently handle safety requirements written in LTL (Linear Temporal Logic)

42 ENGINEERING↗

Introduction: Neuromorphic Materials

The explosive growth in data collection and the need to process it efficiently, as well as the desire to automate increasingly complex tasks in transportation, medical care, manufacturing, security and many other fields have motivated a growing interest in neuromorphic computing. Unlike the binary, transistorbased ON/OFF logic gates and separate logic and memory functionalities employed in digital computing, neuromorphic computing is inspired by animal brains that use interconnected synapses and neurons to perform processing, storage and transmission of information at the same location, while only consuming ~20 W or less of power. Motivated by the brain’s efficiency, adaptability, self-learning and resiliency qualities, neuromorphic computing can be broadly defined as an approach to processing and storing information using hardware and algorithms inspired by models of biological neural systems. Present research in neuromorphic computing encompasses approaches that vary significantly in their degree of neuro-inspiration, from systems that only incorporate features such as asynchronous, event-driven operation or use crossbar arrays of non-volatile memory (NVM) elements to accelerate deep neural networks (DNNs), to designs that embrace the extreme parallelism, sparsity, reconfigurability, adaptability, complexity and stochasticity observed in nervous systems. The term ‘neuromorphic’ computing is often credited to Carver Mead, who in the 1980s investigated Si-based analog electronics to replicate functions of the animal retina. Earlier important advances in this field include the work of Frank Rosenblatt, who proposed the concept of the perceptron, Bernard Widrow, who used this concept to build one of the first analog neural networks, the Adaline and many other researchers (see ref. 6 for an historical perspective on neuromorphic computing). With the recent increase in the use of artificial intelligence and large language models, and rising concerns over the associated energy costs, interest in neuromorphic hardware has expanded rapidly. According to some estimates, driven largely by the drastic growth in the training use of artificial intelligence (AI) models using the current computing architectures, the energy cost of computing is projected to reach the energy supply worldwide by 2045. Furthermore, while this is not a realistic outcome, it means that, if more efficient computing technologies are not developed -- soon -- the world will soon become one where demand for energy and market constraints limit the continued increase of societal access to AI and cloud services from data centers. Data centers used for training and use of these models consume hundreds of terawatt hours of electricity, already past 4% of the US electricity demand.

Circuits↗