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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Magellan spacecraft and memory state tracking: Lessons learned, future thoughts

Numerous studies have been dedicated to improving the two main elements of Spacecraft Mission Operations: Command and Telemetry. As a result, not much attention has been given to other tasks that can become tedious, repetitive, and error prone. One such task is Spacecraft and Memory State Tracking, the process by which the status of critical spacecraft components, parameters, and the contents of on-board memory are managed on the ground to maintain knowledge of spacecraft and memory states for future testing, anomaly investigation, and on-board memory reconstruction. The task of Spacecraft and Memory State Tracking has traditionally been a manual task allocated to Mission Operations Procedures. During nominal Mission Operations this job is tedious and error prone. Because the task is not complex and can be accomplished manually, the worth of a sophisticated software tool is often questioned. However, in the event of an anomaly which alters spacecraft components autonomously or a memory anomaly such as a corrupt memory or flight software error, an accurate ground image that can be reconstructed quickly is a priceless commodity. This study explores the process of Spacecraft and Memory State Tracking used by the Magellan Spacecraft Team highlighting its strengths as well as identifying lessons learned during the primary and extended missions, two memory anomalies, and other hardships encountered due to incomplete knowledge of spacecraft states. Ideas for future state tracking tools that require minimal user interaction and are integrated into the Ground Data System will also be discussed.

Bucher, Allen W.↗
NASA NTRS1993

A petabyte size electronic library using the N-Gram memory engine

A model library containing petabytes of data is proposed by Triada, Ltd., Ann Arbor, Michigan. The library uses the newly patented N-Gram Memory Engine (Neurex), for storage, compression, and retrieval. Neurex splits data into two parts: a hierarchical network of associative memories that store 'information' from data and a permutation operator that preserves sequence. Neurex is expected to offer four advantages in mass storage systems. Neurex representations are dense, fully reversible, hence less expensive to store. Neurex becomes exponentially more stable with increasing data flow; thus its contents and the inverting algorithm may be mass produced for low cost distribution. Only a small permutation operator would be recalled from the library to recover data. Neurex may be enhanced to recall patterns using a partial pattern. Neurex nodes are measures of their pattern. Researchers might use nodes in statistical models to avoid costly sorting and counting procedures. Neurex subsumes a theory of learning and memory that the author believes extends information theory. Its first axiom is a symmetry principle: learning creates memory and memory evidences learning. The theory treats an information store that evolves from a null state to stationarity. A Neurex extracts information data without a priori knowledge; i.e., unlike neural networks, neither feedback nor training is required. The model consists of an energetically conservative field of uniformly distributed events with variable spatial and temporal scale, and an observer walking randomly through this field. A bank of band limited transducers (an 'eye'), each transducer in a bank being tuned to a sub-band, outputs signals upon registering events. Output signals are 'observed' by another transducer bank (a mid-brain), except the band limit of the second bank is narrower than the band limit of the first bank. The banks are arrayed as n 'levels' or 'time domains, td.' The banks are the hierarchical network (a cortex) and transducers are (associative) memories. A model Neurex was built and studied. Data were 50 MB to 10 GB samples of text, data base, and images: black/white, grey scale, and high resolution in several spectral bands. Memories at td, S(m(sub td)), were plotted against outputs of memories at td-1. S(m(sub td)) was Boltzman distributed, and memory frequencies exhibited self-organized criticality (SOC); i.e., 'l/f(sup beta)' after long exposures to data. Whereas output signals from level n may be encoded with B(sub output) = O(-log(2)f(sup beta)) bits, and input data encoded with B(sub input) = O((S(td)/S(td-1))(sup n)), B(sup output)/B(sub input) is much less than 1 always, the Neurex determines a canonical code for data and it is a lossless data compressor. Further tests are underway to confirm these results with more data types and larger samples.

Bugajski, Joseph M.↗
NASA NTRS2001

Future Development of Dense Ferroelectric Memories for Space Applications

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Philpy, Stephen C.↗
NASA NTRS2004

Hold-up power supply for flash memory

A hold-up power supply for flash memory systems is provided. The hold-up power supply provides the flash memory with the power needed to temporarily operate when a power loss exists. This allows the flash memory system to complete any erasures and writes, and thus allows it to shut down gracefully. The hold-up power supply detects when a power loss on a power supply bus is occurring and supplies the power needed for the flash memory system to temporally operate. The hold-up power supply stores power in at least one capacitor. During normal operation, power from a high voltage supply bus is used to charge the storage capacitors. When a power supply loss is detected, the power supply bus is disconnected from the flash memory system. A hold-up controller controls the power flow from the storage capacitors to the flash memory system. The hold-up controller uses feedback to assure that the proper voltage is provided from the storage capacitors to the flash memory system. This power supplied by the storage capacitors allows the flash memory system to complete any erasures and writes, and thus allows the flash memory system to shut down gracefully.

Ott, William E.↗
DOE OSTI2025

Harnessing ferro-valleytricity in pentalayer rhombohedral graphene for memory and compute

Two-dimensional materials with multiple degrees of freedom, including spin, valleys, and orbitals, open up an exciting avenue for engineering multifunctional devices. Beyond spintronics, these degrees of freedom can lead to novel quantum effects such as valley-dependent Hall effects and orbital magnetism, which could revolutionize next-generation electronics. However, achieving independent control over valley polarization and orbital magnetism has been a challenge due to the need for large electric fields. A recent breakthrough involving pentalayer rhombohedral graphene has demonstrated the ability to individually manipulate anomalous Hall signals and orbital magnetic hysteresis, forming what is known as a valley-magnetic quartet. Here, we leverage the electrically tunable ferro-valleytricity of pentalayer rhombohedral graphene to develop nonvolatile memory and in-memory computation applications. We propose an architecture for a dense, scalable, and selector-less nonvolatile memory array that harnesses the electrically tunable ferro-valleytricity. In our designed array architecture, nondestructive read and write operations are conducted by sensing the valley state through two different pairs of terminals, allowing for independent optimization of read/write peripheral circuits. The power consumption of our PRG-based array is remarkably low, with only ∼6 nW required per write operation and ∼2.3 nW per read operation per cell. This consumption is orders of magnitude lower than that of the majority of state-of-the-art cryogenic memories. Additionally, we engineer in-memory computation by implementing majority logic operations within our proposed nonvolatile memory array without modifying the peripheral circuitry. In conclusion, our framework presents a promising pathway toward achieving ultra-dense cryogenic memory and in-memory computation capabilities.

2D materials↗
DOE OSTI2024

The ECP SICM project: Managing complex memory hierarchies for exascale applications

The Exascale Computing Project (ECP)’s Simplified Interface to Complex Memories (SICM) effort focuses on developing universal interfaces for discovering, managing, and sharing data across complex memory hierarchies. These facilitate the exploitation of emerging memory technologies and support precise control over their various trade-offs such as high-bandwidth versus low-latency, persistent versus ephemeral, high-capacity versus low-capacity, and near-CPU versus near-GPU. SICM comprises three interrelated components: a low-level interface, a high-level interface, and a persistent-heap interface. The low-level SICM interface is intended for system and run-time developers as well as expert application developers who prefer full control of the memory objects used within their application. The high-level SICM interface builds upon the low-level interface, employing application-level profiling and analysis to optimize data management for complex memory hierarchies. The persistent-heap interface provides applications with a persistent memory allocator that can allocate custom C++ data structures in both block-storage and byte-addressable persistent memories.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Addressing Issues with Working Memory in Video Object Segmentation

Contemporary state-of-the-art video object segmentation (VOS) models compare incoming unannotated images to a history of image-mask relations via affinity or cross-attention to predict object masks. We refer to the internal memory state of the initial image-mask pair and past image-masks as a working memory buffer. While the current state of the art models perform very well on clean video data, their reliance on a working memory of previous frames leaves room for error. Affinity-based algorithms include the inductive bias that there is temporal continuity between consecutive frames. To account for inconsistent camera views of the desired object, working memory models need an algorithmic modification that regulates the memory updates and avoid writing irrelevant frames into working memory. A simple algorithmic change is proposed that can be applied to any existing working memory-based VOS model to improve performance on inconsistent views, such as sudden camera cuts, frame interjections, and extreme context changes. The resulting model performances show significant improvement on video data with these frame interjections over the same model without the algorithmic addition. Our contribution is a simple decision function that determines whether working memory should be updated based on the detection of sudden, extreme changes and the assumption that the object is no longer in frame. By implementing algorithmic changes, such as this, we can increase the real-world applicability of current VOS models.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1983

Distributed multiport memory architecture

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

Kohl, W. H.↗
NASA NTRS1986

Is random access memory random?

Most software is contructed on the assumption that the programs and data are stored in random access memory (RAM). Physical limitations on the relative speeds of processor and memory elements lead to a variety of memory organizations that match processor addressing rate with memory service rate. These include interleaved and cached memory. A very high fraction of a processor's address requests can be satified from the cache without reference to the main memory. The cache requests information from main memory in blocks that can be transferred at the full memory speed. Programmers who organize algorithms for locality can realize the highest performance from these computers.

Denning, P. J.↗
NASA NTRS1990

Recognition of simple visual images using a sparse distributed memory: Some implementations and experiments

Previously, a method was described of representing a class of simple visual images so that they could be used with a Sparse Distributed Memory (SDM). Herein, two possible implementations are described of a SDM, for which these images, suitably encoded, will serve both as addresses to the memory and as data to be stored in the memory. A key feature of both implementations is that a pattern that is represented as an unordered set with a variable number of members can be used as an address to the memory. In the 1st model, an image is encoded as a 9072 bit string to be used as a read or write address; the bit string may also be used as data to be stored in the memory. Another representation, in which an image is encoded as a 256 bit string, may be used with either model as data to be stored in the memory, but not as an address. In the 2nd model, an image is not represented as a vector of fixed length to be used as an address. Instead, a rule is given for determining which memory locations are to be activated in response to an encoded image. This activation rule treats the pieces of an image as an unordered set. With this model, the memory can be simulated, based on a method of computing the approximate result of a read operation.

Jaeckel, Louis A.↗
NASA NTRS1986

The Science of Computing: Virtual Memory

In the March-April issue, I described how a computer's storage system is organized as a hierarchy consisting of cache, main memory, and secondary memory (e.g., disk). The cache and main memory form a subsystem that functions like main memory but attains speeds approaching cache. What happens if a program and its data are too large for the main memory? This is not a frivolous question. Every generation of computer users has been frustrated by insufficient memory. A new line of computers may have sufficient storage for the computations of its predecessor, but new programs will soon exhaust its capacity. In 1960, a longrange planning committee at MIT dared to dream of a computer with 1 million words of main memory. In 1985, the Cray-2 was delivered with 256 million words. Computational physicists dream of computers with 1 billion words. Computer architects have done an outstanding job of enlarging main memories yet they have never kept up with demand. Only the shortsighted believe they can.

Denning, Peter J.↗
NASA NTRS2001

Space Radiation Effects in Advanced Flash Memories

Memory storage requirements in space systems have steadily increased, much like storage requirements in terrestrial systems. Large arrays of dynamic memories (DRAMs) have been used in solid-state recorders, relying on a combination of shielding and error-detection-and correction (EDAC) to overcome the extreme sensitivity of DRAMs to space radiation. For example, a 2-Gbit memory (with 4-Mb DRAMs) used on the Clementine mission functioned perfectly during its moon mapping mission, in spite of an average of 71 memory bit flips per day from heavy ions. Although EDAC worked well with older types of memory circuits, newer DRAMs use extremely complex internal architectures which has made it increasingly difficult to implement EDAC. Some newer DRAMs have also exhibited catastrophic latchup. Flash memories are an intriguing alternative to DRAMs because of their nonvolatile storage and extremely high storage density, particularly for applications where writing is done relatively infrequently. This paper discusses radiation effects in advanced flash memories, including general observations on scaling and architecture as well as the specific experience obtained at the Jet Propulsion Laboratory in evaluating high-density flash memories for use on the NASA mission to Europa, one of Jupiter's moons. This particular mission must pass through the Jovian radiation belts, which imposes a very demanding radiation requirement.

Johnston, A. H.↗
NASA NTRS2007

Assessing the Effects of Momentary Priming on Memory Retention During an Interference Task

A memory aid, that used brief (33ms) presentations of previously learned information (target words), was assessed on its ability to reinforce memory for target words while the subject was performing an interference task. The interference task required subjects to learn new words and thus interfered with their memory of the target words. The brief presentation (momentary memory priming) was hypothesized to refresh the subjects memory of the target words. 143 subjects, in a within subject design, were given a 33ms presentation of the target memory words during the interference task in a treatment condition and a blank 33ms presentation in the control condition. The primary dependent measure, memory loss over the interference trial, was not significantly different between the two conditions. The memory prime did not appear to hinder the subjects performance on the interference task. This paper describes the experiment and the results along with suggestions for future research.

Schutte, Paul C.↗
NASA NTRS2000

Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order

A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.

Wulf, William A.↗
NASA NTRS2011

AC Electric Field Activated Shape Memory Polymer Composite

Shape memory materials have drawn interest for applications like intelligent medical devices, deployable space structures and morphing structures. Compared to other shape memory materials like shape memory alloys (SMAs) or shape memory ceramics (SMCs), shape memory polymers (SMPs) have high elastic deformation that is amenable to tailored of mechanical properties, have lower density, and are easily processed. However, SMPs have low recovery stress and long response times. A new shape memory thermosetting polymer nanocomposite (LaRC-SMPC) was synthesized with conductive fillers to enhance its thermo-mechanical characteristics. A new composition of shape memory thermosetting polymer nanocomposite (LaRC-SMPC) was synthesized with conductive functionalized graphene sheets (FGS) to enhance its thermo-mechanical characteristics. The elastic modulus of LaRC-SMPC is approximately 2.7 GPa at room temperature and 4.3 MPa above its glass transition temperature. Conductive FGSs-doped LaRC-SMPC exhibited higher conductivity compared to pristine LaRC SMP. Applying an electric field at between 0.1 Hz and 1 kHz induced faster heating to activate the LaRC-SMPC s shape memory effect relative to applying DC electric field or AC electric field at frequencies exceeding1 kHz.

Kang, Jin Ho↗
NASA NTRS2011

Initial Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite

The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite that launched in November 2010. The memory device being tested is a commercial Ramtron Inc. 512K memory device. The circuit was designed into the satellite avionics and is not used to control the satellite. The test consists of writing and reading data with the ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is sent to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test is one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The initial data from the test is presented. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.

MacLeond, Todd C.↗
NASA NTRS2018

A Study of Shape Memory Polymer Based Slat-Cove Filler

Aircraft noise reduction is an application of current intense interest for which smart materials show significant potential. Specifically, the aeroacoustic noise produced by the unsteady aerodynamic flow about the leading-edge high-lift device, such as leading-edge slat, of typical transport-aircraft wings is of particular interest. Concepts with the most promise to mitigate this noise source, most notably the slat-cove filler concept, have focused on highly reconfigurable structures that change shape between different phases of the flight envelope. These shape changes often involve large deformation, which has stimulated the consideration of shape memory materials. In recent years, shape memory materials (SMMs) have drawn greater interest for applications such as smart fabrics, intelligent medical devices, self-deployable space structures, morphing structures and packaging. Compared to other shape memory materials, like shape memory alloys (SMAs) or shape memory ceramics (SMCs), shape memory polymers (SMPs) have desirable advantages such as high elastic deformation to enable large shape change, broad tailorability of mechanical properties, potential biocompatibility and biodegradability, ductility, light weight and ease of processing. However, SMPs still have some critical disadvantages such as insufficient mechanical and thermal characteristics for structural applications, low recovery stress, and long response time. The new LaRC shape memory thermosetting polymer composite (LaRC-SMPC) discussed herein was synthesized with nontoxic monomers and conductive/magnetic fillers to yield enhanced thermal/mechanical characteristics and faster response times. LaRC-SMPCs with a variety of fiber reinforcements [Kevlar®, carbon fiber (standard and thin-ply), and carbon-nanotube (CNT) sheet] were fabricated to tailor the physical properties and test for suitability as a slat-cove filler (SCF). The performance of SCF prototypes fabricated with the developed LaRC-SMPCs was evaluated using a bench-top test apparatus. The SCFs made of Kevlar® fiber fabric or carbon fiber fabric infused shape memory polymer composite (SMPC) exhibited kinking during simulated deployment and stowage, which can be problematic during operation. The SCF made of CNT sheet/SMP composite did not exhibit kinking, but the deployment was sluggish compared to carbon fiber fabric/SMP composite. This report documents the evolution of designing SMPCs as slat-cove fillers for aircraft noise reduction. In the course of the investigation, several 2 approaches were investigated to address shortcomings in material characteristics based on performance requirements of operational slat-cove fillers.

Kang, Jin Ho↗
DOE OSTI2025

A Study on the Impact of Temperature-Dependent Ferroelectric Switching Behavior in 3D Memory Architecture

The flourishing development of neural networks that require exponentially growing amounts of data has presented an elevated demand for memory footprint. To address this, researchers have been exploring hardware accelerators with innovative memory architectures like 3D memory. These 3D memory architectures offer enhanced storage capacity and processing capabilities, at a cost of rising on-chip temperature during operation. Hafnium Zirconium Oxide (HZO) based Ferroelectric Random Access Memory (FeRAM) is a promising nonvolatile memory candidate in neural network hardware accelerators for its outstanding write performance and reliability. However, its implementation in the architecture regarding the temperature-dependent ferroelectric switching behavior has not been well studied. In this work, we study the thermal impacts on polarization switching through experimental devices and simulation results. We conduct the circuit and architecture-level simulations to showcase that one can exploit this temperature rise to reduce FeRAM's write voltage and write energy due to its unique temperature-activated polarization switching mechanisms. As the on-chip temperature increases to 351K (ambient temperature at 300K) due to neural network workloads, the access energy per bit can be reduced by 27.6% when a dynamic write voltage is applied.

36 MATERIALS SCIENCE↗