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At least 73 records · Page 4

High Performance Parallel Computational Nanotechnology

At a recent press conference, NASA Administrator Dan Goldin encouraged NASA Ames Research Center to take a lead role in promoting research and development of advanced, high-performance computer technology, including nanotechnology. Manufacturers of leading-edge microprocessors currently perform large-scale simulations in the design and verification of semiconductor devices and microprocessors. Recently, the need for this intensive simulation and modeling analysis has greatly increased, due in part to the ever-increasing complexity of these devices, as well as the lessons of experiences such as the Pentium fiasco. Simulation, modeling, testing, and validation will be even more important for designing molecular computers because of the complex specification of millions of atoms, thousands of assembly steps, as well as the simulation and modeling needed to ensure reliable, robust and efficient fabrication of the molecular devices. The software for this capacity does not exist today, but it can be extrapolated from the software currently used in molecular modeling for other applications: semi-empirical methods, ab initio methods, self-consistent field methods, Hartree-Fock methods, molecular mechanics; and simulation methods for diamondoid structures. In as much as it seems clear that the application of such methods in nanotechnology will require powerful, highly powerful systems, this talk will discuss techniques and issues for performing these types of computations on parallel systems. We will describe system design issues (memory, I/O, mass storage, operating system requirements, special user interface issues, interconnects, bandwidths, and programming languages) involved in parallel methods for scalable classical, semiclassical, quantum, molecular mechanics, and continuum models; molecular nanotechnology computer-aided designs (NanoCAD) techniques; visualization using virtual reality techniques of structural models and assembly sequences; software required to control mini robotic manipulators for positional control; scalable numerical algorithms for reliability, verifications and testability. There appears no fundamental obstacle to simulating molecular compilers and molecular computers on high performance parallel computers, just as the Boeing 777 was simulated on a computer before manufacturing it.

Saini, Subhash↗

Evaluation of Galvanic Vestibular Stimulation System

Microgravity exposure results in an adaptive central reinterpretation of information from multiple sensory sources to produce a sensorimotor state appropriate for motor actions in this unique environment, but this new adaptive state is no longer appropriate for the 1-g gravitational environment on Earth. During these gravitational transitions, astronauts experience deficits in both perceptual and motor functions including impaired postural control, disruption in spatial orientation, impaired control of locomotion that include alterations in muscle activation variability, modified lower limb kinematics, alterations in head-trunk coordination as well as reduced dynamic visual acuity. Post-flight changes in postural and locomotor control might have adverse consequences if a rapid egress was required following a long-duration mission, where support personnel may not be available to aid crewmembers. The act of emergency egress includes, but is not limited to standing, walking, climbing a ladder, jumping down, monitoring displays, actuating discrete controls, operating auxiliary equipment, and communicating with Mission Control and recovery teams while maintaining spatial orientation, mobility and postural stability in order to escape safely. The average time to recover impaired postural control and functional mobility to preflight levels of performance has been shown to be approximately two weeks after long-duration spaceflight. The postflight alterations are due in part to central reinterpretation of vestibular information caused by exposure to microgravity. In this study we will use a commonly used technique of transcutaneous electrical stimulation applied across the vestibular end organs (galvanic vestibular stimulation, GVS) to disrupt vestibular function as a simulation of post-flight disturbances. The goal of this project is an engineering human-in-the-loop evaluation of a device that can degrade performance of functional tasks (e.g. to maintain upright balance) similar to what astronauts experience during transitions to new gravitational environments. Stochastic electrical stimulation can be applied to the vestibular system through electrodes placed over the mastoid process behind the ears in the binaural configuration resulting in stimulation in the mediolateral (side-to-side) plane. An additional electrode can be placed over the bony landmark of the tip of the c7 spinous process for the double monaural configuration, which will cause stimulation in the anteroposterior (forward-backward) plane. A portable constant current bipolar stimulator with subject isolation was designed and built to deliver the stimulus. The unit is powered using a 3.7 V battery pack and designed to produce currents up to 5 mA. The stimulator, controlled by a Raspberry Pi 3 computer, offers several stimulus signal generation options including a standalone mode, which uses onboard signal files stored on the flash memory card. Stochastic stimulation signals will be generated in 0-30 Hz frequency bandwidth. Stimulation amplitude can be increased incrementally to a maximum amplitude of 5.0 mA (e.g., 0, 0.5, 1.0, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0 mA). In control trials, subjects will be experiencing vestibular stimulation with 0-mA current applied through the electrodes. The system will be evaluated at various levels of stimulation and in both the binaural and double monaural electrode configurations. One of the objectives is to identify stimulation levels producing effects most comparable to the post-flight disturbances. This is a pilot study that will set the stage for a larger, more comprehensive study that will investigate wider aspects of post-flight sensorimotor dysfunction and set sensorimotor standards for crew health.

Kofman, I. S.↗

Intelligent Memory Module Overcomes Harsh Environments

Solar cells, integrated circuits, and sensors are essential to manned and unmanned space flight and exploration, but such systems are highly susceptible to damage from radiation. Especially problematic, the Van Allen radiation belts encircle Earth in concentric radioactive tori at distances from about 6,300 to 38,000 km, though the inner radiation belt can dip as low as 700 km, posing a severe hazard to craft and humans leaving Earth s atmosphere. To avoid this radiation, the International Space Station and space shuttles orbit at altitudes between 275 and 460 km, below the belts range, and Apollo astronauts skirted the edge of the belts to minimize exposure, passing swiftly through thinner sections of the belts and thereby avoiding significant side effects. This radiation can, however, prove detrimental to improperly protected electronics on satellites that spend the majority of their service life in the harsh environment of the belts. Compact, high-performance electronics that can withstand extreme environmental and radiation stress are thus critical to future space missions. Increasing miniaturization of electronics addresses the need for lighter weight in launch payloads, as launch costs put weight at a premium. Likewise, improved memory technologies have reduced size, cost, mass, power demand, and system complexity, and improved high-bandwidth communication to meet the data volume needs of the next-generation high-resolution sensors. This very miniaturization, however, has exacerbated system susceptibility to radiation, as the charge of ions may meet or exceed that of circuitry, overwhelming the circuit and disrupting operation of a satellite. The Hubble Space Telescope, for example, must turn off its sensors when passing through intense radiation to maintain reliable operation. To address the need for improved data quality, additional capacity for raw and processed data, ever-increasing resolution, and radiation tolerance, NASA spurred the development of the Radiation Tolerant Intelligent Memory Stack (RTIMS).

Source record↗

Direct strike lightning measurement system

A research data system developed for in-flight measurement of direct and nearby lightning-strike characteristics is described. The measurement system consists of a wide-band analog recorder which records the continuous lightning scenario and fast sample-rate digital transient recorders with augmented memory capacity for increased time resolution of specific times of interest. Electromagnetic sensors with bandwidths exceeding 100 MHz are used which respond to rates of change of the quantities being measured. Data system immunity from electromagnetic interference is accomplished by the use of a dynamotor for power isolation, shielded system enclosure and fiber-optic data links.

Thomas, M. E.↗

The SGI/Cray T3E: Experiences and Insights

The NASA Goddard Space Flight Center is home to the fifth most powerful supercomputer in the world, a 1024 processor SGI/Cray T3E-600. The original 512 processor system was placed at Goddard in March, 1997 as part of a cooperative agreement between the High Performance Computing and Communications Program's Earth and Space Sciences Project (ESS) and SGI/Cray Research. The goal of this system is to facilitate achievement of the Project milestones of 10, 50 and 100 GFLOPS sustained performance on selected Earth and space science application codes. The additional 512 processors were purchased in March, 1998 by the NASA Earth Science Enterprise for the NASA Seasonal to Interannual Prediction Project (NSIPP). These two "halves" still operate as a single system, and must satisfy the unique requirements of both aforementioned groups, as well as guest researchers from the Earth, space, microgravity, manned space flight and aeronautics communities. Few large scalable parallel systems are configured for capability computing, so models are hard to find. This unique environment has created a challenging system administration task, and has yielded some insights into the supercomputing needs of the various NASA Enterprises, as well as insights into the strengths and weaknesses of the T3E architecture and software. The T3E is a distributed memory system in which the processing elements (PE's) are connected by a low latency, high bandwidth bidirectional 3-D torus. Due to the focus on high speed communication between PE's, the T3E requires PE's to be allocated contiguously per job. Further, jobs will only execute on the user specified number of PE's and PE timesharing is possible but impractical. With a highly varied job mix in both size and runtime of jobs, the resulting scenario is PE fragmentation and an inability to achieve near 100% utilization. SGI/Cray has provided several scheduling and configuration tools to minimize the impact of fragmentation. These tools include PScheD (the political scheduler), GRM (the global resource manager) and NQE (the Network Queuing Environment). Features and impact of these tools will be discussed, as will resulting performance and utilization data. As a distributed memory system, the T3E is designed to be programmed through explicit message passing. Consequently, certain assumptions related to code design are made by the operating system (UNICOS/mk) and its scheduling tools. With the exception of HPF, which does run on the T3E, however poorly, alternative programming styles have the potential to impact the T3E in unexpected and undesirable ways. Several examples will be presented (preceeded with the disclaimer, "Don't try this at home! Violators will be prosecuted!")

Bernard, Lisa Hamet↗

Precision waveform shaping and precompensation for high data rate space coomunications systems

This paper studies a memory-based pulse shaping and traveling wave tube precompensation technique applied to high data rate satellite communications. Baseband I and Q waveforms are synthesized from data stored in a distributed arithmetic architecture. The waveforms are adjusted to minimize intersymbol interference spectral bandwidth and traveling wave tube distortion. We evaluate its performance in a simulated bi-phase shift keying (BPSK) link. The results show that memory-based precompensation has great potential to improve link performance.

Tague, John A.↗

A 10 micron heterodyne receiver for ultra high resolution astronomical spectroscopy

An improved CO2 laser heterodyne spectrometer is examined. The present system uses reflective optics to eliminate refocusing at different wavelengths, and the local oscillator is a line-center-stabilized isotopic CO2 laser. A tunable diffraction grating makes possible easy and rapid selection of over 50 transitions per isotope of CO2. The IF (0 to 1.6 GHz) from the HgCdTe photomizer is analyzed by a 128-channel filter bank, consisting of 64 tunable 5-MHz filters and 64 fixed 25-MHz RF filters. These filters provide resolving powers of about 1,000,000 to 10,000,000 and velocity resolution of 50 to 250 m/sec; their output is synchronously detected, integrated, multiplexed and stored in a buffer memory for the desired integration period. Kitt Peak observations show the wide spectral coverage, wide mixer and electronics bandwidth, and high sensitivity of the system.

Buhl, D.↗

Requirements and Usage of NVM in Advanced Onboard Data Processing Systems

This viewgraph presentation gives an overview of the requirements and uses of non-volatile memory (NVM) in advanced onboard data processing systems. Supercomputing in space presents the only viable approach to the bandwidth problem (can't get data down to Earth), controlling constellations of cooperating satellites, reducing mission operating costs, and real-time intelligent decision making and science data gathering. Details are given on the REE vision and impact on NASA and Department of Defense missions, objectives of REE, baseline architecture, and issues. NVM uses and requirements are listed.

Some, R.↗

Interconnect Performance Evaluation of SGI Altix 3700 BX2, Cray X1, Cray Opteron Cluster, and Dell PowerEdge

We study the performance of inter-process communication on four high-speed multiprocessor systems using a set of communication benchmarks. The goal is to identify certain limiting factors and bottlenecks with the interconnect of these systems as well as to compare these interconnects. We measured network bandwidth using different number of communicating processors and communication patterns, such as point-to-point communication, collective communication, and dense communication patterns. The four platforms are: a 512-processor SGI Altix 3700 BX2 shared-memory machine with 3.2 GB/s links; a 64-processor (single-streaming) Cray XI shared-memory machine with 32 1.6 GB/s links; a 128-processor Cray Opteron cluster using a Myrinet network; and a 1280-node Dell PowerEdge cluster with an InfiniBand network. Our, results show the impact of the network bandwidth and topology on the overall performance of each interconnect.

Fatoohi, Rod↗

Effects of ISI and satellite channel nonlinearity on Viterbi demodulation/decoding

It is shown that, for convolutionally coded transmission over bandwidth-constrained channels, a mere reversal of the switching direction at the encoder output produces a change in the system bit error probability performance. This change is significant when the Viterbi demodulator/decoder is matched to the total channel memory and is more significant for linear channels than for nonlinear ones. The reversal of switching direction is a simple demonstration of the fact that the well-known optimum codes for the linear AGWN channel are no longer necessarily optimum for a bandwidth-constrained channel with or without the addition of channel nonlinearity. It is concluded that potentially significant performance improvement can be obtained by matching the encoder (through the appropriate choice of tap weights and modulo-2 summers) to the channel in addition to matching the demodulator/decoder to the channel for a given encoder.

Divsalar, D.↗

Low-Power Architectures for Large Radio Astronomy Correlators

The architecture of a cross-correlator for a synthesis radio telescope with N greater than 1000 antennas is studied with the objective of minimizing power consumption. It is found that the optimum architecture minimizes memory operations, and this implies preference for a matrix structure over a pipeline structure and avoiding the use of memory banks as accumulation registers when sharing multiply-accumulators among baselines. A straw-man design for N = 2000 and bandwidth of 1 GHz, based on ASICs fabricated in a 90 nm CMOS process, is presented. The cross-correlator proper (excluding per-antenna processing) is estimated to consume less than 35 kW.

signal processing↗

Optimization of a Solver for Computational Materials and Structures Problems on NVIDIA Volta and AMD Instinct GPUs

The Scalable Implementation of Finite Elements by NASA (ScIFEN) is a software package developed to solve complex computational materials and structures problems using the finite element method (FEM). In this paper, we describe optimization techniques to speed up the linear solver computation that occurs within the ScIFEN application. We consider GPUs from two different vendors, NVIDIA and AMD as our target platforms for optimization and highlight differences in performance and optimization techniques. The NVIDIA GPU Volta V100 is used in the Summit system deployed at Oak Ridge National Laboratory, and the new exascale system, Frontier, will be using AMD Radeon Instinct GPU. We evaluated the performance of various optimization techniques on test matrices, ranging in size from100K to 4M, that are representative of ScIFEN applications. The linear solver computation is memory-bound on both GPUs. Our experiments show that on the NVIDIA GPU we obtained up to79%of the theoretical peak bandwidth, while the AMD GPU achieved 59%. Overall, the NVIDIA V100 GPU outperforms the AMD MI 25 GPU1. We observed an overall speedup of up to37X on an NVIDIA V100 compared to an Intel Skylake 12-coremachine. The solver for a 4M degree of freedom system took under 2.5 seconds.

Mohammad Zubair↗

Coarse-Grain Bandwidth Estimation Scheme for Large-Scale Network

A large-scale network that supports a large number of users can have an aggregate data rate of hundreds of Mbps at any time. High-fidelity simulation of a large-scale network might be too complicated and memory-intensive for typical commercial-off-the-shelf (COTS) tools. Unlike a large commercial wide-area-network (WAN) that shares diverse network resources among diverse users and has a complex topology that requires routing mechanism and flow control, the ground communication links of a space network operate under the assumption of a guaranteed dedicated bandwidth allocation between specific sparse endpoints in a star-like topology. This work solved the network design problem of estimating the bandwidths of a ground network architecture option that offer different service classes to meet the latency requirements of different user data types. In this work, a top-down analysis and simulation approach was created to size the bandwidths of a store-and-forward network for a given network topology, a mission traffic scenario, and a set of data types with different latency requirements. These techniques were used to estimate the WAN bandwidths of the ground links for different architecture options of the proposed Integrated Space Communication and Navigation (SCaN) Network. A new analytical approach, called the "leveling scheme," was developed to model the store-and-forward mechanism of the network data flow. The term "leveling" refers to the spreading of data across a longer time horizon without violating the corresponding latency requirement of the data type. Two versions of the leveling scheme were developed: 1. A straightforward version that simply spreads the data of each data type across the time horizon and doesn't take into account the interactions among data types within a pass, or between data types across overlapping passes at a network node, and is inherently sub-optimal. 2. Two-state Markov leveling scheme that takes into account the second order behavior of the store-and-forward mechanism, and the interactions among data types within a pass. The novelty of this approach lies in the modeling of the store-and-forward mechanism of each network node. The term store-and-forward refers to the data traffic regulation technique in which data is sent to an intermediate network node where they are temporarily stored and sent at a later time to the destination node or to another intermediate node. Store-and-forward can be applied to both space-based networks that have intermittent connectivity, and ground-based networks with deterministic connectivity. For groundbased networks, the store-and-forward mechanism is used to regulate the network data flow and link resource utilization such that the user data types can be delivered to their destination nodes without violating their respective latency requirements.

Cheung, Kar-Ming↗

Onward to Petaflops Computing

With the recent demonstration of a computing rate of one Tflop/s at Sandia National Lab, one might ask what lies ahead for high-end computing. The next major milestone is a sustained rate of one Pflop/s (also written one petaflops, or 10(exp 15) floating-point operations per second). It should be emphasized that we could just as well use the term "peta-ops", since it appears that large scientific systems will be required to perform intensive integer and logical computation in addition to floating-point operations, and completely non- floating-point applications are likely to be important as well. In addition to prodigiously high computational performance, such systems must of necessity feature very large main memories, between ten Tbyte (10(exp 13) byte) and one Pbyte (10 (exp 15) byte) depending on application, as well as commensurate I/O bandwidth and huge mass storage facilities. The current consensus of scientists who have performed initial studies in this field is that "affordable" petaflops systems may be feasible by the year 2010, assuming that certain key technologies continue to progress at current rates. A sustained petaflops computing capability however is a daunting challenge; it appears significantly more challenging from today's state-of-the-art than achieving one Tflop/s has been from the level of one Gflop/s about 12 years ago. Challenges are faced in the arena of device technology, system architecture, system software, algorithms and applications. This talk will give an overview of some of these challenges, and describe some of the recent initiatives to address them.

Bailey, David H.↗

High Performance Programming Using Explicit Shared Memory Model on Cray T3D1

The Cray T3D system is the first-phase system in Cray Research, Inc.'s (CRI) three-phase massively parallel processing (MPP) program. This system features a heterogeneous architecture that closely couples DEC's Alpha microprocessors and CRI's parallel-vector technology, i.e., the Cray Y-MP and Cray C90. An overview of the Cray T3D hardware and available programming models is presented. Under Cray Research adaptive Fortran (CRAFT) model four programming methods (data parallel, work sharing, message-passing using PVM, and explicit shared memory model) are available to the users. However, at this time data parallel and work sharing programming models are not available to the user community. The differences between standard PVM and CRI's PVM are highlighted with performance measurements such as latencies and communication bandwidths. We have found that the performance of neither standard PVM nor CRI s PVM exploits the hardware capabilities of the T3D. The reasons for the bad performance of PVM as a native message-passing library are presented. This is illustrated by the performance of NAS Parallel Benchmarks (NPB) programmed in explicit shared memory model on Cray T3D. In general, the performance of standard PVM is about 4 to 5 times less than obtained by using explicit shared memory model. This degradation in performance is also seen on CM-5 where the performance of applications using native message-passing library CMMD on CM-5 is also about 4 to 5 times less than using data parallel methods. The issues involved (such as barriers, synchronization, invalidating data cache, aligning data cache etc.) while programming in explicit shared memory model are discussed. Comparative performance of NPB using explicit shared memory programming model on the Cray T3D and other highly parallel systems such as the TMC CM-5, Intel Paragon, Cray C90, IBM-SP1, etc. is presented.

Simon, Horst D.↗

The Use of Field Programmable Gate Arrays (FPGA) in Small Satellite Communication Systems

This paper will describe the use of digital Field Programmable Gate Arrays (FPGA) to contribute to advancing the state-of-the-art in software defined radio (SDR) transponder design for the emerging SmallSat and CubeSat industry and to provide advances for NASA as described in the TAO5 Communication and Navigation Roadmap (Ref 4). The use of software defined radios (SDR) has been around for a long time. A typical implementation of the SDR is to use a processor and write software to implement all the functions of filtering, carrier recovery, error correction, framing etc. Even with modern high speed and low power digital signal processors, high speed memories, and efficient coding, the compute intensive nature of digital filters, error correcting and other algorithms is too much for modern processors to get efficient use of the available bandwidth to the ground. By using FPGAs, these compute intensive tasks can be done in parallel, pipelined fashion and more efficiently use every clock cycle to significantly increase throughput while maintaining low power. These methods will implement digital radios with significant data rates in the X and Ka bands. Using these state-of-the-art technologies, unprecedented uplink and downlink capabilities can be achieved in a 1/2 U sized telemetry system. Additionally, modern FPGAs have embedded processing systems, such as ARM cores, integrated inside the FPGA allowing mundane tasks such as parameter commanding to occur easily and flexibly. Potential partners include other NASA centers, industry and the DOD. These assets are associated with small satellite demonstration flights, LEO and deep space applications. MSFC currently has an SDR transponder test-bed using Hardware-in-the-Loop techniques to evaluate and improve SDR technologies.

Varnavas, Kosta↗

Considerations of digital phase modulation for narrowband satellite mobile communication

The Inmarsat-M system for mobile satellite communication is specified as a frequency division multiple access (FDMA) system, applying Offset Quadrature Phase Shift Keying (QPSK) for transmitting 8 kbit/sec in 10 kHz user channel bandwidth. We consider Digital Phase Modulation (DPM) as an alternative modulation format for INMARSAT-M. DPM is similar to Continuous Phase Modulation (CPM) except that DPM has a finite memory in the premodular filter with a continuous varying modulation index. It is shown that DPM with 64 states in the VA obtains a lower bit error rate (BER). Results for a 5 kHz system, with the same 8 kbit/sec transmitted bitstream, is also presented.

Grythe, Knut↗

Cross-Cutting Flight Infrastructure Improvements on M2020

Mars2020 (M2020) was formulated as a mission that leveraged as much Mars Science Laboratory (MSL) heritage as possible, while focusing major new development efforts on the original and unique elements needed to accomplish the different mission objectives. Well publicized examples of high profile new developments include precision landing, the sampling and caching system, the specific instrument suite, improved mobility via Autonomous Navigation, and later the addition of the Ingenuity helicopter. Less well known are the refinements to the core flight infrastructure, primarily in the cross-cutting functions of Telecom, Avionics, Data Management, Communications Behaviors, and Parameter Management. These enhancements are introduced predominately via flight software, and represent increases in capability that justified their inclusion in an otherwise heritage-focused project environment.Perseverance’s cross-cutting flight infrastructure improvements fall into and across the following five categories. First is a trimming of the software footprint of infrastructure modules, in order to make room for memory demands elsewhere in the system. Second is the minimization of data volume to be downlinked, through various methods such as the incorporation of new compression options. Third is the maximization of the available downlink bandwidth for data, by curtailing content-less data (fill) and introducing an improved UHF proximity link protocol. Fourth is a reduction in vulnerabilities, through increased file system redundancy, robustness, and software process monitoring. Fifth is an increase in operations efficiency by lowering file system mount times, improving parallelism between simultaneous events, minimizing the time to recover from file system errors, streamlining the purging of obsolete data, and reducing the number of commands to service parameters by a factor of 100.Individually, none of the cross-cutting infrastructure improvements are likely to garner headlines, but collectively they appreciably improve the safety and operability of Perseverance over its predecessor. This paper will describe the improvements, their promise, and where applicable, their actual impact in operations.

Bohannon, Emily↗