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At least 73 records · Page 4

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DOE OSTI2026

Paradigm for universal quantum information processing with integrated acousto-optic frequency beamsplitters

Frequency-bin encoding offers tremendous potential in quantum photonic information processing, in which a single waveguide can support hundreds of lightpaths in a naturally phase-stable fashion. This stability, however, comes at a cost: arbitrary unitary operations can be realized by cascaded electro-optic phase modulators and pulse shapers, but require nontrivial numerical optimization for design and have thus far been limited to discrete tabletop components. In this article, we propose, formalize, and computationally evaluate a new paradigm for universal frequency-bin quantum information processing using acousto-optic scattering processes between distinct transverse modes. We show that controllable phase matching in intermodal processes enables 2 × 2 frequency beamsplitters and transverse-mode-dependent phase shifters, which together comprise cascadable FRequency-transverse-mODe Operations (FRODOs) that can synthesize any unitary via analytical decomposition procedures. Modeling the performance of both random gates and discrete Fourier transforms, we demonstrate the feasibility of high-fidelity quantum operations with existing integrated photonics technology, highlighting prospects of parallelizable operations achieving 100% bandwidth utilization. Our approach is realizable with CMOS technology, opening the door to scalable on-chip quantum information processing in the frequency domain.

Lukens, Joseph M. [Purdue Univ., West Lafayette, I↗

DOE OSTI2025

Integrated Coulomb Blockade Thermometry for Quantum Computing

In our work we present on-chip thermometry concept aimed at improving temperature control during quantum measurements. The key issue addressed is lack of precise temperature monitoring, especially considering the unavoidable thermal resistance between the qubits’ chip and mixing plate of dilution refrigerator. The suggested solution includes a Coulomb Blockade Thermometer (CBT) based on an array of intrinsically normal-conducting tunnel junctions, currently developed at Aalto University. This is a practical solution for superconducting qubit systems.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2025

SPT-SLIM: Line-Intensity Mapping Pathfinder on the South Pole Telescope

The Shirokoff Line-Intensity Mapper (SPT-SLIM) is a mm-wavelength, superconducting on-chip spectrometer observing redshifted CO in the 2mm atmospheric window using the 10-meter South Pole Telescope (SPT). The instrument was recently deployed for the first time during the 2024-2025 austral summer season at South Pole, where it conducted a short two-week observing campaign. We will present an overview of the SPT-SLIM instrument and project, discuss early results from its initial deployment, and preview the prospects for a longer survey using upgraded instrumentation in the 2025-2026 austral summer.

Anderson, Adam [Fermilab; Chicago U.]↗

DOE OSTI2025

Cryogenic Performance of the SPT-SLIM Receiver

The South Pole Telescope Shirokoff Line Intensity Mapper (SPT-SLIM) is a millimeter-wave line-intensity mapping experiment, deployed on the South Pole Telescope (SPT) during the 2024-2025 Austral Summer season. This pathfinder experiment serves to demonstrate the on-sky operation of multi-pixel on-chip spectrometer technology. We present on the cryogenic performance of the SPT-SLIM receiver for this Year 1 observing campaign. The SPT-SLIM receiver utilizes an Adiabatic Demagnetization Referigerator (ADR) for cooling the focal plane of superconducting filterbank spectrometers to a temperature of 150mK. We demonstrate stable thermal performance of the focal plane module during observing operations in line with thermal modelling, enabling a cryogenic operation efficiency above 80%. We also report on the receiver control system design utilizing the Observatory Control System (OCS) platform for automated cryogenic operation on the SPT.

Young, Matthew [Fermilab]↗

DOE OSTI2025

Frequency and time multiplexing for multiphoton state generation

One of the primary challenges with photonic quantum information processing is that single-photon states are created and heralded probabilistically, rather than being created on demand. One solution to this problem is multiplexing , which is attempting probabilistic generation of a single photon at multiple locations, times, or frequencies, and switching one successfully generated photon into an output mode. Motivated by the development of frequency-based photonic quantum information processing, we consider multiplexing using frequency and time as our options to use to get many photon generation opportunities. We devise an approach for generating multiphoton states, with photons populating multiple frequency modes in the same spatiotemporal mode. This method uses a variable-length optical delays to manipulate the temporal mode of the photons, and spaced fiber Bragg grating (FBG) reflectors to jointly manipulate the frequency and temporal modes of the photons. Experimental progress toward implementing this multiplexing scheme is proceeding along 2 fronts, each with different ways to achieve the variable-length optical delay. First, we will implement this scheme using a free-space optical quantum memory with multiple discretely adjustable free-space delays. For this implementation method, I calculate multiphoton generation rates, accounting for loss, that are realistically achievable with commercially available hardware. This work will appear in a theory paper, currently in preparation. Second, we will implement this multiplexing scheme in an integrated manner: the variable-length optical delay will happen on-chip using a long-lifetime Q-switchable Fabry-Perot cavity. The joint manipulation of the frequency and temporal modes of the photons will still happen off-chip in fiber with FBG reflectors. I report on experimental progress in constructing integrated Q-switchable Fabry-Perot cavities.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Improved Charge Sensing on a SiMOS Double Quantum Dot using a Cryogenic Skipper Readout ASIC (Quandarum)

Major outstanding questions in high-energy physics such as the nature of dark matter and the existence of interactions beyond the standard model require new measurement techniques which are extremely sensitive to minute electromagnetic fields. An array of entangled spin qubits is a promising system for building novel detectors due to its combination of sensitivity and controllability. CMOS-based electron spin qubits, which have demonstrated the operational requirements for fault-tolerant quantum computing [1], offer a particular opportunity due to their compatibility with classical electronics, which allows the leveraging of decades of development of low-noise cryogenic detectors for physics. In this work, we combine a SiMOS double-quantum dot device architecture with a state-of-the-art cryoelectronic readout circuit [2-3] aimed to demonstrate improved charge readout using a single-electron transistor (SET). We identify the design characteristics for an SET that facilitate the use of on-chip classical electronics as a low-power, high-bandwidth first amplification stage and explore opportunities for sensor-readout co-design to minimize noise. This is the first of a series of steps to demonstrate high-fidelity readout of a large array of spin qubit with enough sensitivity to probe processes of interest for the investigation of beyond-standard-model physics.

Quinn, Adam [Fermilab]↗

DOE OSTI2026

A Compact Monolithic Electro-Optic Package for Quantum Microwave-to-Optical Transduction

We present a novel quantum transduction package that integrates a macroscopic electro-optic crystal into a compact, monolithic assembly designed for superconducting quantum processors. The device provides an efficient and scalable interface between microwave and optical domains while preserving cryogenic compatibility. We performed full-wave and quantum dynamical simulations to assess the performance of the hybrid system, focusing on the interaction between a transmon-based microwave cavity and the crystal’s and cavity low-frequency microwave mode. The transmon operates both as an ancilla for the QPU and as a nonlinear element enabling four-wave mixing between cavity and electro-optic crystal microwave fields. Our results indicate that this architecture can coherently mediate quantum information transfer from the cavity to the electro-optic mode, offering a promising platform for on-chip quantum transduction within superconducting quantum networks.

Reineri, Alessandro [Fermilab] (ORCID:000000016175↗

DOE OSTI2026

A Compact Monolithic Electro-Optic Package for Quantum Microwave-to-Optical Transduction

Reineri, Alessandro [Fermilab] (ORCID:000000016175↗

DOE OSTI2026

Digital Silicon Photomultiplier Chip Testing

Silicon Photomultipliers (SiPMs) are highly sensitive photodetectors. Traditional analog SiPMs require complex external readout electronics. Digital SiPMs (dSiPMs) include digital readout circuitry directly on-chip, offering superior timing resolution, reduced power consumption and compact size, pixel-level masking for active noise reduction. The primary objectives of this study are to, verify digital logic integrity of the shift registers used for controlling the pixel masking circuit, and determine the dark count rate of individual pixels as a function of bias voltage and clock frequency. I observe and explain behavior of the shift register and counting circuit.

Graham, Bennett [U. Chicago (main)]↗

DOE OSTI2026

Bio-Inspired Energy-Efficient Nanofabricated Electrical Contacts

Nanoscale electrical contacts, especially those between materials of dissimilar electronic properties, often represent one of the main causes of drops in energy transfer efficiency. They are also among the sources of above-threshold noise, and their performance often decreases over the lifetime of the nanodevices. Scale-down limitations from mesoscopic to nanoscale devices, and likewise, of nanoscale to quantum-scale devices are also impeded by contacts’ quality. Making more reliable, energy-efficient electrical contacts is among the goals of the nanoelectronics research within the framework of energy-efficient electronic systems. This report focuses on the design, nanofabrication, and testing of novel shapes of electrical contacts. Lithography and nanofabrication were utilized to mimic the approximate shape of insect setae for mesoscale contacts design. The contacts are tested for elementary charge transport via I–V curves and for the broadband, 1/f noise. Tests show that contacts design leads to a measurable decrease in the energy necessary to operate a contact as a switch by at least 12–20%, depending on temperature, while broadband noise shows measurably lower power spectra, for bio-inspired contacts. The proposed method is open to modifications and improvements as required by various on-chip applications.

36 MATERIALS SCIENCE↗

DOE OSTI2025

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems

Domain-specific systems improve the performance of a specific set of applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration to optimize the compute performance of the generated accelerators. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how the accelerators access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8x performance improvements while lowering memory channel utilization on average by 53.2% for a set of PolyBench kernels.

Limaye, Ankur M. (ORCID:0000000194062584)↗

DOE OSTI2025

Design and Performance of the SPT-SLIM Receiver Cryostat

The South Pole Telescope Shirokoff Line Intensity Mapper (SPT-SLIM) is a millimeter-wavelength line-intensity mapping experiment, which was deployed on the South Pole Telescope (SPT) during the 2024-2025 Austral summer season. This pathfinder experiment serves to demonstrate the on-sky operation of multi-pixel on-chip spectrometer technology. We report on the cryogenic performance of the SPT-SLIM receiver for the first year of commissioning observations. The SPT-SLIM receiver utilizes an Adiabatic Demagnetization Refrigerator (ADR) for cooling the focal plane of superconducting filterbank spectrometers to a temperature of 150 mK. We demonstrate stable thermal performance of the focal plane module during observations consistent with thermal modeling, enabling a cryogenic operating efficiency above 80%. We also report on the receiver control system design utilizing the Observatory Control System (OCS) platform for automated cryogenic operation on the SPT.

Young, M. R. [Fermilab; Chicago U., KICP]↗

DOE OSTI2025

An On-Sky Atmospheric Calibration of SPT-SLIM

We present the methodology and results of the on-sky responsivity calibration of the South Pole Telescope Shirokoff Line Intensity Mapper (SPT-SLIM). SPT-SLIM is a pathfinder line intensity mapping experiment utilizing the on-chip spectrometer technology, and was first deployed during the 2024-2025 Austral Summer season on the South Pole Telescope. During the two-week on-sky operation of SPT-SLIM, we performed periodic measurements of the detector response as a function of the telescope elevation angle. Combining these data with atmospheric opacity measurements from an on-site atmospheric tipping radiometer, simulated South Pole atmospheric spectra, and measured detector spectral responses, we construct estimates for the responsivity of SPT-SLIM detectors to sky loading. We then use this model to calibrate observations of the moon taken by SPT-SLIM, cross-checking the result against the known brightness temperature of the Moon as a function of its phase.

Dibert, K. R. [Chicago U., Astron. Astrophys. Ctr.↗

DOE OSTI2025

Obsidian

Obsidian A35 is a compact FPGA carrier board designed to interface with ADCs, DACs or other devices, either stand-alone or as an I/O expansion board. The connectivity includes 1 GigE, 4 SFP, 6 PMOD, FTDI USB and Arduino shield compatible header. The board features also a FPGA boot SPI Flash, on-chip DDR3 memory, VCXO and White Rabbit compatibility.

Moore, Victoria [Lawrence Berkeley National Labora↗

DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗

DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

Alcalde Bessia, Fabricio↗

DOE OSTI2026

A 3D-Printed Millimeter-Wave Inline Waveguide-to-Coplanar-Waveguide Transition to Enable Dense Spectrometer Arrays for Intensity Mapping Surveys

We present a 3D-printed millimeter-wave, octave-bandwidth, in-line waveguide-to-coplanar-waveguide transition designed to enable focal planes with dense arrays of on-chip spectrometers. These arrays will enable compelling surveys of the large-scale structure of the universe through millimeter-wave intensity mapping. The transition consists of a four-step ridge-waveguide transformer that couples light from a rectangular waveguide onto a coplanar waveguide via an electrical connection made with indium bump bonds. We develop a tolerance-aware optimization approach to identify high-performance transition geometries that are robust to manufacturing variations; the same formulation can be applied to other tolerance-sensitive design problems. We also describe the implementation of a custom apparatus and procedure for bump-bonding a silicon chip to a metallized 3D-printed component. We detail the fabrication of the coplanar waveguide chip and three-dimensional waveguide structure, simulations and metrology of a test device, and room temperature reflectance measurements of this device. The room temperature metrology and reflection measurements are consistent with a model that predicts a coupling efficiency of $\mathord{\sim} 95\%$ at cryogenic temperatures in the 85-170 GHz frequency range.