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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1976

Irradiate-anneal screening of total dose effects in semiconductor devices

An extensive investigation of irradiate-anneal (IRAN) screening against total dose radiation effects was carried out as part of a program to harden the Mariner Jupiter/Saturn 1977 (MJS'77) spacecraft to survive the Jupiter radiation belts. The method consists of irradiating semiconductor devices with Cobalt-60 to a suitable total dose under representative bias conditions and of separating the parts in the undesired tail of the distribution from the bulk of the parts by means of a predetermined acceptance limit. The acceptable devices are then restored close to their preirradiation condition by annealing them at an elevated temperature. IRAN was used when lot screen methods were impracticable due to lack of time, and when members of a lot showed a diversity of radiation response. The feasibility of the technique was determined by testing of a number of types of linear bipolar integrated circuits, analog switches, n-channel JFETS and bipolar transistors. Based on the results of these experiments a number of device types were selected for IRAN of flight parts in the MJS'77 spacecraft systems. The part types, screening doses, acceptance criteria, number of parts tested and rejected as well as the program steps are detailed.

Stanley, A. G.↗
NASA NTRS1995

Non-parabolic hydrodynamic formulations for the simulation of inhomogeneous semiconductor devices

Hydrodynamic models are becoming prevalent design tools for small scale devices and other devices in which high energy effects can dominate transport. Most current hydrodynamic models use a parabolic band approximation to obtain fairly simple conservation equations. Interest in accounting for band structure effects in hydrodynamic device simulation has begun to grow since parabolic models can not fully describe the transport in state of the art devices due to the distribution populating non-parabolic states within the band. This paper presents two different non-parabolic formulations of the hydrodynamic model suitable for the simulation of inhomogeneous semiconductor devices. The first formulation uses the Kane dispersion relationship (hk)(exp 2)/2m = W(1 + alpha(W)). The second formulation makes use of a power law ((hk)(exp 2)/2m = xW(sup y)) for the dispersion relation. Hydrodynamic models which use the first formulation rely on the binomial expansion to obtain moment equations with closed form coefficients. This limits the energy range over which the model is valid. The power law formulation readily produces closed form coefficients similar to those obtained using the parabolic band approximation. However, the fitting parameters (x,y) are only valid over a limited energy range. The physical significance of the band non-parabolicity is discussed as well as the advantages/disadvantages and approximations of the two non-parabolic models. A companion paper describes device simulations based on the three dispersion relationships: parabolic, Kane dispersion, and power low dispersion.

Smith, Arlynn W.↗
NASA NTRS1996

Non-Parabolic Hydrodynamic Formulations for the Simulation of Inhomogeneous Semiconductor Devices

Hydrodynamic models are becoming prevalent design tools for small scale devices and other devices in which high energy effects can dominate transport. Most current hydrodynamic models use a parabolic band approximation to obtain fairly simple conservation equations. Interest in accounting for band structure effects in hydrodynamic device simulation has begun to grow since parabolic models cannot fully describe the transport in state of the art devices due to the distribution populating non-parabolic states within the band. This paper presents two different non-parabolic formulations or the hydrodynamic model suitable for the simulation of inhomogeneous semiconductor devices. The first formulation uses the Kane dispersion relationship ((hk)(exp 2)/2m = W(1 + alphaW). The second formulation makes use of a power law ((hk)(exp 2)/2m = xW(exp y)) for the dispersion relation. Hydrodynamic models which use the first formulation rely on the binomial expansion to obtain moment equations with closed form coefficients. This limits the energy range over which the model is valid. The power law formulation readily produces closed form coefficients similar to those obtained using the parabolic band approximation. However, the fitting parameters (x,y) are only valid over a limited energy range. The physical significance of the band non-parabolicity is discussed as well as the advantages/disadvantages and approximations of the two non-parabolic models. A companion paper describes device simulations based on the three dispersion relationships; parabolic, Kane dispersion and power law dispersion.

Smith, A. W.↗
NASA NTRS1995

Method for fabricating semiconductor devices

A process for fabricating gold/gallium arsenide structures, in situ, on molecular beam epitaxially grown gallium arsenide. The resulting interface proves to be Ohmic, an unexpected result which is interpreted in terms of increased electrode interdiffusion. More importantly, the present invention surprisingly permits the fabrication of Ohmic contacts in a III-V semiconductor material at room temperature. Although it may be desireable to heat the Ohmic contact to a temperature of, for example, 200 degrees Centigrade if one wishes to further decrease the resistance of the contact, such low temperature annealing is much less likely to have any deleterious affect on the underlying substrate. The use of the term in situ herein, contemplates continuously maintaining an ultra-high vacuum, that is a vacuum which is at least 10.sup.-8 Torr, until after the metallization has been completed. An alternative embodiment of the present invention comprising an additional step, namely the termination of the gallium arsenide by a two monolayer thickness of epitaxial aluminum arsenide as a diffusion barrier, enables the recovery of Schottky barrier behavior, namely a rectified I-V characteristic. The present invention provides a significant breakthrough in the fabrication of III-V semiconductor devices wherein excellent Ohmic contact and Schottky barrier interfaces to such devices can be achieved simply and inexpensively and without requiring the high temperature processing of the prior art and also without requiring the use of exotic high temperature refractory materials as substitutes for those preferred contact metals such as gold, aluminum and the like.

Kaiser, William J.↗
NASA NTRS1993

Optimal convolution SOR acceleration of waveform relaxation with application to semiconductor device simulation

In this paper we describe a novel generalized SOR (successive overrelaxation) algorithm for accelerating the convergence of the dynamic iteration method known as waveform relaxation. A new convolution SOR algorithm is presented, along with a theorem for determining the optimal convolution SOR parameter. Both analytic and experimental results are given to demonstrate that the convergence of the convolution SOR algorithm is substantially faster than that of the more obvious frequency-independent waveform SOR algorithm. Finally, to demonstrate the general applicability of this new method, it is used to solve the differential-algebraic system generated by spatial discretization of the time-dependent semiconductor device equations.

Reichelt, Mark↗
NASA NTRS1979

Procedure for pressure contact on high-power semiconductor devices free of thermal fatigue

To eliminate thermal fatigue, a procedure for manufacturing semiconductor power devices with pure pressure contact without solid binding was developed. Pressure contact without the use of a solid binding to avoid a limitation of the maximum surface in the contact was examined. A silicon wafer covered with a relatively thick metal layer is imbedded with the aid of a soft silver foil between two identically sized hard contact discs (molybdenum or tungsten) which are rotationally symmetrical. The advantages of this concept are shown for large diameters. The pressure contact was tested successfully in many devices in a large variety of applications.

Knobloch, J.↗
NASA NTRS1970

Power semiconductor device with negative thermal feedback

Composite power semiconductor avoids second breakdown and provides stable operation. It consists of an array of parallel-connected integrated circuits fabricated in a single chip. The output power device and associated low-level amplifier are closely coupled thermally, so that they have a predetermined temperature relationship.

Borky, J. M.↗
NASA NTRS1993

Demonstration of Y1Ba2Cu3O(7-delta) and complementary metal-oxide-semiconductor device fabrication on the same sapphire substrate

We report the first fabrication of active semiconductor and high-temperature superconducting devices on the same substrate. Test structures of complementary MOS transistors were fabricated on the same sapphire substrate as test structures of Y1Ba2Cu3O(7-delta) flux-flow transistors, and separately, Y1Ba2Cu3O(7-delta) superconducting quantum interference devices utilizing both biepitaxial and step-edge Josephson junctions. Both semiconductor and superconductor devices were operated at 77 K. The cofabrication of devices using these disparate yet complementary electronic technologies on the same substrate opens the door for the fabrication of true semiconductive/superconductive hybrid integrated circuits capable of exploiting the best features of each of these technologies.

Burns, M. J.↗
NASA NTRS1970

Multiport semiconductor devices

Device, made of a variety of semiconductors, incorporates three or more terminals. Between at least two terminals, switching action occurs. The other terminal pair performs either another switching function or a control function. This device is useful for computer-logic or memory applications.

Holmstrom, F. R.↗
NASA NTRS2011

Pulsed Laser System to Simulate Effects of Cosmic Rays in Semiconductor Devices

Spaceflight system electronic devices must survive a wide range of radiation environments with various particle types including energetic protons, electrons, gamma rays, x-rays, and heavy ions. High-energy charged particles such as heavy ions can pass straight through a semiconductor material and interact with a charge-sensitive region, generating a significant amount of charge (electron-hole pairs) along their tracks. These excess charges can damage the device, and the response can range from temporary perturbations to permanent changes in the state or performance. These phenomena are called single event effects (SEE). Before application in flight systems, electronic parts need to be qualified and tested for performance and radiation sensitivity. Typically, their susceptibility to SEE is tested by exposure to an ion beam from a particle accelerator. At such facilities, the device under test (DUT) is irradiated with large beams so there is no fine resolution to investigate particular regions of sensitivity on the parts. While it is the most reliable approach for radiation qualification, these evaluations are time consuming and costly. There is always a need for new cost-efficient strategies to complement accelerator testing: pulsed lasers provide such a solution. Pulsed laser light can be utilized to simulate heavy ion effects with the advantage of being able to localize the sensitive region of an integrated circuit. Generally, a focused laser beam of approximately picosecond pulse duration is used to generate carrier density in the semiconductor device. During irradiation, the laser pulse is absorbed by the electronic medium with a wavelength selected accordingly by the user, and the laser energy can ionize and simulate SEE as would occur in space. With a tightly focused near infrared (NIR) laser beam, the beam waist of about a micrometer can be achieved, and additional scanning techniques are able to yield submicron resolution. This feature allows mapping of all of the sensitive regions of the studied device with fine resolution, unlike heavy ion experiments. The problematic regions can be precisely identified, and it provides a considerable amount of information about the circuit. In addition, the system allows flexibility for testing the device in different configurations in situ.

Aveline, David C.↗
NASA NTRS1981

Amorphous metallizations for high-temperature semiconductor device applications

The initial results of work on a class of semiconductor metallizations which appear to hold promise as primary metallizations and diffusion barriers for high temperature device applications are presented. These metallizations consist of sputter-deposited films of high T sub g amorphous-metal alloys which (primarily because of the absence of grain boundaries) exhibit exceptionally good corrosion-resistance and low diffusion coefficients. Amorphous films of the alloys Ni-Nb, Ni-Mo, W-Si, and Mo-Si were deposited on Si, GaAs, GaP, and various insulating substrates. The films adhere extremely well to the substrates and remain amorphous during thermal cycling to at least 500 C. Rutherford backscattering and Auger electron spectroscopy measurements indicate atomic diffussivities in the 10 to the -19th power sq cm/S range at 450 C.

Wiley, J. D.↗
NASA NTRS1986

Producing Silicon Carbide for Semiconductor Devices

Processes proposed for production of SiC crystals for use in semiconductors operating at temperatures as high as 900 degrees C. Combination of new processes produce silicon carbide chips containing epitaxial layers. Chips of SiC first grown on porous carbon matrices, then placed in fluidized bed, where additional layer of SiC grows. Processes combined to yield complete process. Liquid crystallization process used to make SiC particles or chips for fluidized-bed process.

Hsu, G. C.↗
NASA NTRS1995

Method for fabricating an interconnected array of semiconductor devices

A method of forming an array of interconnected solar cells. A flexible substrate carrying semiconductor and conductive layers is divided into individual devices by slitting the substrate along the web length. The individual devices are then connected with one another in series by laminating the substrate onto an insulating backing and by depositing conducting interconnection layers which join the lower conductor of one device with the top conductor of the adjoining device.

Grimmer, Derrick P.↗