SEARCH · Search NASA

Results for “Single Event Upset Testing”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 73 records · Page 4

All sources NASA NTRS DOE OSTI

NASA NTRS1992

Single event phenomena: Testing and prediction

Highly integrated microelectronic devices are often used to increase the performance of satellite systems while reducing the system power dissipation, size, and weight. However, these devices are usually more susceptible to radiation than less integrated devices. In particular, the problem of sensitivity to single event upset and latchup is greatly increased as the integration level is increased. Therefore, a method for accurately evaluating the susceptibility of new devices to single event phenomena is critical to qualifying new components for use in space systems. This evaluation includes testing devices for upset or latchup and extrapolating the results of these tests to the orbital environment. Current methods for testing devices for single event effects are reviewed, and methods for upset rate prediction, including a new technique based on Monte Carlo simulation, are presented.

Kinnison, James D.↗

NASA NTRS2018

Xilinx Kintex-UltraScale Field Programmable Gate Array Single Event Effects (SEE) Heavy-Ion Test Report

This is an independent investigation that evaluates the single event destructive and transient susceptibility of the Xilinx Kintex-UltraScale device. Design/Device susceptibility is determined by monitoring the device under test (DUT) for Single Event Transient (SET) and Single Event Upset (SEU) induced faults by exposing the DUT to a heavy ion beam. Potential Single Event Latch-up (SEL) is monitored throughout heavy-ion testing by examining device current. This device does not have embedded mitigation. Hence, user implemented mitigation is investigated using Synopsys mitigation tools.

Single Event Transient (SET)↗

NASA NTRS1993

Experience, lessons learned and methodology in the design of space systems to accommodate total dose and SEU effects

We now have considerable experience with successfully designing science systems to function properly, even during and after exposure to ionizing radiation approaching one Megarad, and during large solar particle events with substantial high Z fluxes such as the events that happened in August, 1972 and in the fall of 1989. Nevertheless, with changing device dimensions and properties, newer technologies and new applications, new problems arise. Some recent basic research has shed light on these problems and pointed the way to better diagnostic tests. In the case of single event upsets, clearly one cannot always accurately predict upset probabilities simply by knowing the quiescent Linear Energy Transfer (LET) threshold and the asymptotic cross-section of the device.

Trainor, James H.↗

NASA NTRS2004

Design Tools for Reconfigurable Hardware in Orbit (RHinO)

The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating software to automatically test and evaluate the single-event-upsets (SEUs) sensitivities of an FPGA design and insert mitigation techniques. Extensions into the tool suite will also allow evolvable algorithm techniques to reconfigure around single-event-latchup (SEL) events. In the power domain, tools are being created for dynamic power visualiization and optimization. Thus, this technology seeks to enable the use of Reconfigurable Hardware in Orbit, via an integrated design tool-suite aiming to reduce risk, cost, and design time of multimission reconfigurable space processors using SRAM-based FPGAs.

French, Mathew↗

NASA NTRS2009

Virtex-4VQ dynamic and mitigated single event upset characterization summary

This report is the result of funding by the NASA Electronic Parts and Packaging Program (NEPP) and the combined efforts of members within the Xilinx Radiation Test Consortium (XRTC), sometimes known as the Xilinx Single Event Effects (SEE) Test Consortium. The XRTC is a voluntary association of aerospace entities, including leading aerospace companies, universitie and national laboratories, combining resources to characterize reconfigurable, field programmable gate arrays (FPGAs) for aerospace applications. Previous publications of Virtex-4 radiation results are for commercial (non-epitaxial) devices; see, for example, Refs. 1–5. A notable exception is Ref. 6, which presents XRTC upset measurements of storage elements in the PowerPC405s in the XQR4VFX60. This work represents a continuation of the efforts reported in the “Virtex-4QV Static SEU Characterization Summary” [7]. The contents of this report describe various Single Event Functional Interrupt (SEFI) and Single Event Upset (SEU) modes seen while dynamically exercising the clocked resources within Virtex-4 devices and the corresponding mitigation techniques related to the aforementioned observed SEFI modes.

Allen, Gregory↗

NASA NTRS1986

The Galileo Attitude and Articulation Control System - A radiation-hard, high precision, state-of-the-art control system

The Galileo Mission and Spacecraft design impose tight requirements on the Attitude and Articulation Control System (AACS). These requirements, coupled with the flexible spacecraft, the need for autonomy, and a severe radiation environment, pose a great challenge for the AACS designer. The resulting design and implementation are described, along with the discovery and solution of the Single-Event Upset problem. The status of the testing of the AACS in the Integration and Test Laboratory as well as at the spacecraft level is summarized.

Rhoads Stephenson, R.↗

NASA NTRS2005

PDSOI and Radiation Effects: An Overview

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.

Forgione, Joshua B.↗

NASA NTRS1991

Test chips and ASIC qualification

A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.

Buehler, M. G.↗

NASA NTRS1991

Multiple single event upsets in CMOS static rams

The occurrence of multiple upset errors during ground tests can contaminate the data and lead to error cross sections which are too high. In space, multiple errors may produce higher upsets than predicted and if they occur in single words they can defeat error detection and correction hardware. This investigation involves data which were taken during an experimental study of dose imprint effects in static memories. The results show that multiple errors occurred mainly for heavy ions with high linear energy transfers and with the majority of these in the soft upset sections of the dose-imprinted memory samples. The percentages of the total number of errors which were singles, doubles, and triplets, were determined as a function of LET, dose, and soft or hard section of the devices. The experimental observations are compared to the predictions of simple binomial statistics.

Stassinopoulos, E. G.↗

NASA NTRS2002

SEE and TID extension testing of the Xilinx XQR18V04 4Mbit radiation hardened configuration PROM

The XQR18V04 was evaluated for single event upset rates using proton and heavy ions. The PROM was demonstrated to be immune to latch-up, as well as to static upset in the flash memory cells, to an LET > 125 MeV/mg/cmz (effective). The PROM was also tested in a dynamic mode, which revealed three distinct error modes: Read Bit Errors, Address Errors, and a Single Event Functional Interrupt (SEW which affected the data output drivers. Saturation cross-sections, and onset thresholds, for these errorinodes were measured at the heavy ion facility at Texas A&M University, and the proton facility at UC Davis. Additional testing was performed at UC Davis and the Cobalt 60 source at McClellan Air Force Base to examine the effect to TID life as a function of power biasing. The PROM demonstrated a 100% improvement in total TID life with an 84% percent decrease in device usage.

FPGA Virtex II SEU↗

NASA NTRS1986

Guidelines for SEU-Resistant Integrated Circuits

Paper presents recent results of continuing program for increasing resistance of integrated circuits to single-event upset (SEU). Results based on study of test data for heavy-ion SEU in more than 180 different types of devices. (Some devices perform identical functions but made by different processes.) Program also examines developments in mathematical models for SEU.

Nichols, D. K.↗

NASA NTRS2018

NASA Electronic Parts and Packaging (NEPP) Field Programmable Gate Array (FPGA) Single Event Effects (SEE) Test Guideline Update

The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.

Test guidelines↗

NASA NTRS2018

NASA Electronic Parts and Packaging Field Programmable Gate Array Single Event Effects Test Guideline Update

Field Programmable Gate Array (FPGA)↗

NASA NTRS2003

Broad Beam and Ion Microprobe Studies of Single-Event Upsets in High Speed 0.18micron Silicon Germanium Heterojunction Bipolar Transistors and Circuits

Combining broad-beam circuit level SEU response with ion microprobe tests on single silicon germanium heterojunction bipolar transistors allows for a better understanding of the charge collection mechanisms responsible for SEU response of HBT technology.

Robert A Reed↗

NASA NTRS1988

Self-Testing Computer Memory

Memory system for computer repeatedly tests itself during brief, regular interruptions of normal processing of data. Detects and corrects transient faults as single-event upsets (changes in bits due to ionizing radiation) within milliseconds after occuring. Self-testing concept surpasses conventional by actively flushing latent defects out of memory and attempting to correct before accumulating beyond capacity for self-correction or detection. Cost of improvement modest increase in complexity of circuitry and operating time.

Chau, Savio, N.↗

NASA NTRS2004

Frequency Dependence of Single-event Upset in Advanced Commerical PowerPC Microprocessors

This paper examines single-event upsets in advanced commercial SOI microprocessors in a dynamic mode, studying SEU sensitivity of General Purpose Registers (GPRs) with clock frequency. Results are presented for SOI processors with feature sizes of 0.18 microns and two different core voltages. Single-event upset from heavy ions is measured for advanced commercial microprocessors in a dynamic mode with clock frequency up to 1GHz. Frequency and core voltage dependence of single-event upsets in registers is discussed.

single-event upset (SEU)↗

NASA NTRS2006

Single Event Effects Test Results for the Actel ProASIC Plus and Altera Stratix-II Field Programmable Gate Arrays

This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.

heavy ions↗

NASA NTRS2004

Single Event Effects in Highly Scaled Devices for Space Applications

This paper discusses single-event upset (SEU) in memories and microprocessors that are the "drivers" of highly scaled commercial integrated circuits. Despite the decrease in critical charge that occurs for highly scaled CMOS devices, recent test data has shown that SEU rates are actually somewhat lower for scaled devices compared to older devices with larger feature size. Hard errors, which are increasingly important for memories, are discussed along with conventional soft errors. Functional errors in memories and microprocessors are particularly significant, and tend to dominate the response of highly scaled devices from an application standpoint. Predictions for future devices are made using the Semiconductor Industry Roadmap along with recent modeling and radiation test results.

microelectronics↗