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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack

Amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack under a maximal processing temperature of 300 {sup o}C. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gate bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E) characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 10{sup 3} P/E cycles, and a memory window of 1.1 V was retained after 10{sup 5} s retention time.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Online thermal profile prediction for large format additive manufacturing: A hybrid CNN-LSTM based approach

Large format additive manufacturing (LFAM) is an advanced 3D printing technique that efficiently fabricates large-scale components through a layer-by-layer extrusion and deposition process. Accurate surface layer temperature monitoring is essential to prevent manufacturing failures and ensure final product quality. Traditional physics-based offline approaches for simulating thermal behavior are often inefficient and complex, posing challenges on real-time, in-situ monitoring. Here, to address this, we propose a data-driven hybrid CNN-LSTM model to predict sequential thermal images of arbitrary length using real-time infrared thermal imaging. In this approach, a Convolutional Neural Networks (CNN) is trained offline to capture spatial features, reduce dimensional complexity, and enhance time efficiency, while a stacked Long Short-Term Memory (LSTM) is applied online to capture temporal information for improved prediction of future thermal behavior in subsequent printing layers. Model performance is evaluated using MSE, SSIM, and PSNR metrics and is benchmarked against stacked LSTM and convolutional LSTM models, demonstrating superior accuracy and applicability. Additionally, to mitigate noise from moving extruders and gantry backgrounds in thermal images, a fine-tuned semantic segmentation model is implemented offline to extract printing geometry, enabling precise temperature tracking along the tool path for further thermal analysis. The frameworks developed in this study significantly advance temperature monitoring, thermal analysis, and in-situ manufacturing control for LFAM, bridging the gap between theoretical modeling and practical application.

Geometry extraction↗
DOE OSTI2015

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

Recent trends of aggressive technology scaling have greatly exacerbated the occurrences and impact of faults in computing systems. This has made `reliability' a first-order design constraint. To address the challenges of reliability, several techniques have been proposed. In this study, we provide a survey of architectural techniques for improving resilience of computing systems. We especially focus on techniques proposed for microarchitectural components, such as processor registers, functional units, cache and main memory etc. In addition, we discuss techniques proposed for non-volatile memory, GPUs and 3D-stacked processors. To underscore the similarities and differences of the techniques, we classify them based on their key characteristics. We also review the metrics proposed to quantify vulnerability of processor structures. Finally, we believe that this survey will help researchers, system-architects and processor designers in gaining insights into the techniques for improving reliability of computing systems.

3D-stacked processors↗
DOE OSTI2023

Predictive model for real-time energy disaggregation using long short-term memory

To provide affordable energy-saving solutions for the small and medium-sized manufacturers (SMMs), we propose a unified framework for generating predictive models that support real-time disaggregation of power consumption from combined inputs, enabling automatic machine state identification simultaneously for joint analysis of energy usage patterns. Further, the proposed framework transforms raw power consumption into a time series with look-back and bootstrap capabilities for historical pattern detection, while a learning architecture utilizes the stacked long short-term memory (LSTM) layers as encoders for embedding generation with sequential awareness. Experimental results demonstrate 93.65% minimum accuracy in ideal case of real-time energy usage and machine state prediction.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2021

Ferroelectric polarization retention with scaling of Hf 0.5 Zr 0.5 O 2 on silicon

In this paper, we investigate the polarization retention of Hf 0.5 Zr 0.5 O 2 (HZO)-based metal–ferroelectric–insulator–Si (MFIS) capacitors with scaling of the ferroelectric (FE) layer thickness from 5 nm to 20 nm. The capacitors have a constant interface layer capacitance of ~24 μF/cm 2 , developed due to the integration of HZO on a degenerated Si as a bottom conducting electrode. It is observed that 20 nm HZO films show a small change (~5%) in FE polarization (P FE ) between short (10 μs) and long (6 s) retention time, while 5-nm-thick films exhibit a large difference (~90%). Furthermore, the dependence of P FE retention loss on the FE thickness can be understood by the presence of a built-in electric field in the FE layer, generated due to charge continuity between the FE and the interface layers in the ground state without any external bias. A direct experimental observation also confirms that a residual voltage is developed at the node between the metal–ferroelectric–metal and metal–oxide–semiconductor capacitors connected in series, in the ground state with zero external bias. It is expected that a proper understanding of the built-in field developed in the FE layer in an MFIS stack is crucial for FE memory retention characteristics.

36 MATERIALS SCIENCE↗
DOE OSTI2016

On the origin of resistive switching volatility in Ni/TiO{sub 2}/Ni stacks

Resistive switching and resistive random access memories have attracted huge interest for next generation nonvolatile memory applications, also thought to be able to overcome flash memories limitations when arranged in crossbar arrays. A cornerstone of their potential success is that the toggling between two distinct resistance states, usually a High Resistive State (HRS) and a Low Resistive State (LRS), is an intrinsic non-volatile phenomenon with the two states being thermodynamically stable. TiO{sub 2} is one of the most common materials known to support non-volatile RS. In this paper, we report a volatile resistive switching in a titanium dioxide thin film sandwiched by two nickel electrodes. The aim of this work is to understand the underlying physical mechanism that triggers the volatile effect, which is ascribed to the presence of a NiO layer at the bottom interface. The NiO layer alters the equilibrium between electric field driven filament formation and thermal enhanced ion diffusion, resulting in the volatile behaviour. Although the volatility is not ideal for non-volatile memory applications, it shows merit for access devices in crossbar arrays due to its high LRS/HRS ratio, which are also briefly discussed.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1994

Three-Dimensional Vertical-Bloch-Line Memory System

In proposed magnetic memory system without moving parts, data is stored in stack of two-dimensional vertical-Bloch-line (VBL) memory chips or modules. System similar to one described in "Three-Dimensional Magnetic-Bubble Memory System" (NPO-18533). Each VBL module in this memory system silimar to module described in "Vertical-Bloch-Line Memory" (NPO-18467). Advantages include high storage density, high speed, nonvolatility, and insensitivity to ionizing radiation.

Katti, Romney R.↗
DOE OSTI2022

Learning the Temporal Effect in Infrared Thermal Videos With Long Short-Term Memory for Quality Prediction in Resistance Spot Welding

With the advances of sensing technology, in-situ infrared thermal videos can be collected from Resistance Spot Welding (RSW) processes. Each video records the formulation process of a weld nugget. The nugget evolution creates a “temporal effect” across the frames, which can be leveraged for real-time, nondestructive evaluation (NDE) of the weld quality. Currently, quality prediction with imaging data mainly focuses on optical feature extraction with Convolutional Neural Network (CNN) but does not make the most of such temporal effect. In this study, pixels corresponding to critical locations on the weld nugget surface are extracted from a video to form multivariate time series (MTS). Multivariate Adaptive Regression Splines (MARS) is used in MTS processing to remove noisy signals related to uninformative frames. A Stacked Long Short-Term Memory (LSTM) model is developed to learn from the processed MTS and then predicts weld nugget size and thickness in real-time NDE. Results from a case study on RSW of Boron steel demonstrates the improvement in prediction accuracy and computational time with the proposed method, as compared to CNN-based weld quality prediction.

Guo, Shenghan↗
DOE OSTI2022

Low-temperature processed beta-phase In 2 Se 3 ferroelectric semiconductor thin film transistors

As scaling becomes increasingly difficult, there is growing interest in vertical or three-dimensional stacking of transistors and especially memory. Ferroelectric semiconductor field effect transistors can be key enablers to improve energy efficiency and overall chip and memory performance. In this work, low-temperature processed, back-end-of-the-line compatible transistors were demonstrated by depositing a layered chalcogenide ferroelectric semiconductor, beta-phase In 2 Se 3 , at temperature as low as 400 °C. Top gate n-channel In 2 Se 3 thin film transistors were fabricated with field-effect mobility ∼1 cm 2 V −1 s −1 , and simple polarization switching based memory results are presented.

36 MATERIALS SCIENCE↗
DOE OSTI2018

PIMS: Memristor-Based Processing-in-Memory-and-Storage.

Continued progress in computing has augmented the quest for higher performance with a new quest for higher energy efficiency. This has led to the re-emergence of Processing-In-Memory (PIM) ar- chitectures that offer higher density and performance with some boost in energy efficiency. Past PIM work either integrated a standard CPU with a conventional DRAM to improve the CPU- memory link, or used a bit-level processor with Single Instruction Multiple Data (SIMD) control, but neither matched the energy consumption of the memory to the computation. We originally proposed to develop a new architecture derived from PIM that more effectively addressed energy efficiency for high performance scientific, data analytics, and neuromorphic applications. We also originally planned to implement a von Neumann architecture with arithmetic/logic units (ALUs) that matched the power consumption of an advanced storage array to maximize energy efficiency. Implementing this architecture in storage was our original idea, since by augmenting storage (in- stead of memory), the system could address both in-memory computation and applications that accessed larger data sets directly from storage, hence Processing-in-Memory-and-Storage (PIMS). However, as our research matured, we discovered several things that changed our original direc- tion, the most important being that a PIM that implements a standard von Neumann-type archi- tecture results in significant energy efficiency improvement, but only about a O(10) performance improvement. In addition to this, the emergence of new memory technologies moved us to propos- ing a non-von Neumann architecture, called Superstrider, implemented not in storage, but in a new DRAM technology called High Bandwidth Memory (HBM). HBM is a stacked DRAM tech- nology that includes a logic layer where an architecture such as Superstrider could potentially be implemented.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Tracing and Forecasting Metabolic Indices of Cancer Patients Using Patient-Specific Deep Learning Models

We develop a patient-specific dynamical system model from the time series data of the cancer patient’s metabolic panel taken during the period of cancer treatment and recovery. The model consists of a pair of stacked long short-term memory (LSTM) recurrent neural networks and a fully connected neural network in each unit. It is intended to be used by physicians to trace back and look forward at the patient’s metabolic indices, to identify potential adverse events, and to make short-term predictions. When the model is used in making short-term predictions, the relative error in every index is less than 10% in the L ∞ norm and less than 6.3% in the L 1 norm in the validation process. Once a master model is built, the patient-specific model can be calibrated through transfer learning. As an example, we obtain patient-specific models for four more cancer patients through transfer learning, which all exhibit reduced training time and a comparable level of accuracy. This study demonstrates that this modeling approach is reliable and can deliver clinically acceptable physiological models for tracking and forecasting patients’ metabolic indices.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2025

Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory

In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.

42 ENGINEERING↗
NASA NTRS1995

The Impact on Space Radiation Requirements and Effects on ASIMS

The evolution of highly miniaturized electronic and mechanical systems will be accompanied by new problems and issues regarding the radiation response of these systems in the space environment. In this paper we discuss some of the more prominent radiation problems brought about by miniaturization. For example, autonomous micro-spacecraft will require large amounts of high density memory, most likely in the form of stacked, multichip modules of DRAM's, that must tolerate the radiation environment. However, advanced DRAM's (16 to 256 Mbit) are quite susceptible to radiation, particularly single event effects, and even exhibit new radiation phenomena that were not a problem for older, less dense memory chips. Another important trend in micro-spacecraft electronics is toward the use of low-voltage microelectronic systems that consume less power. However, the reduction in operating voltage also caries with it an increased susceptibility to radiation. In the case of application specific integrated microcircuits (ASIM's), advanced devices of this type, such as high density field programmable gate arrays (FPGA's) exhibit new single event effects (SEE), such as single particle reprogramming of anti-fuse links. New advanced bipolar circuits have been shown recently to degrade more rapidly in the low dose rate space environment than in the typical laboratory total dose radiation test used to qualify such devices. Thus total dose testing of these parts is no longer an appropriately conservative measure to be used for hardness assurance. We also note that the functionality of micromechanical Si-based devices may be altered due to the radiation-induced deposition of charge in the oxide passivation layers.

Barnes, C.↗
NASA NTRS2020

Micron MT29F1T08CMHBBJ4 1Tb NAND Flash Memory Single Event Effect Characterization Test Report

The purpose of this testing is to characterize the Single-Event Effect (SEE) response of the Micron MT29F1T08CMHBBJ4 3D NAND Flash memory. The MT29F1T08CMHBBJ4 is a 1Tb NAND Flash memory, consisting of a four-die stack of 256Gb MLC dice packaged in a 132-ball VBGA package. All data presented is the result of testing only the top die (256Gb) of the package. Testing was performed at two heavy-ion cyclotron facilities with an identical test setup, over the course of four test trips from 2017-2019.

Single Event Effect (SEE)↗
DOE OSTI2017

Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, High Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions “near-memory,” and if user-addressable, “scratchpad.” High-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Here, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Lamellar: A Rust-based Asynchronous Tasking and PGAS Runtime for High Performance Computing

Cybersecurity is one of the largest concerns in modern computing, impacting and dictating how governments, private corporations, and individuals interact with and live in an increasingly digital world. The NSA has recently released a memo [ 1] on “Software Memory Safety” where they highlight that both Microsoft and Google have stated around 70% of software vulnerabilities were due to memory safety issues. Although languages such as C and C++ provide freedom and flexibility with memory management, guaran- teeing safety falls mostly on the developer. The NSA recommends using “memory safe” languages whenever possible. In this paper we introduce Lamellar, an asynchronous tasking and PGAS HPC runtime written in Rust, one such "memory safe" language. We describe the entire Lamellar stack, from network interfaces to high- level abstractions such as distributed LamellarArrays and Active Messages. We conclude by showing comparable performance to legacy PGAS runtimes (e.g. OpenSHMEM) on a subset of the BALE kernel suite while maintaining strong memory safety principles.

HPC Software Systems, Rust Programming Language, P↗
DOE OSTI2020

Layer-Dependent Bit Error Variation in 3-D NAND Flash Under Ionizing Radiation

In this paper, we studied the total ionization dose (TID) effects on the multilevel-cell (MLC) 3-D NAND flash memory using Co-60 gamma radiation. We found a significant page-to-page bit error variation within a physical memory block of the irradiated memory chip. Our analysis showed that the origin of the bit error variation is the unique vertical layer-dependent TID response of the 3-D NAND. We found that the memory pages located at the upper and lower layers of the 3-D stack show higher fails compared to the middle-layer pages of a given memory block. We confirmed our findings by comparing radiation response of four different chips of the same specification. In addition, we compared the TID response of the MLC 3-D NAND with that of the 2-D NAND chip, which showed less page-to-page variation in bit error within a given memory block. We discuss the possible application of our findings for the radiation-tolerant smart memory controller design.

3-D NAND flash↗
DOE OSTI2021

A simulation study of carbon storage with active reservoir management

As part of the Integrated Midcontinent Stacked Carbon Storage Hub (IMSCS-Hub) project led by Battelle Memorial Institute, a study was conducted to determine the feasibility of storing carbon dioxide (CO 2 ) in the stacked saline rock formations of the Sleepy Hollow Field (SHF), located in Red Willow County, southern Nebraska. A series of CO 2 injection simulation scenarios, with and without active reservoir management (ARM; brine extraction), were evaluated to investigate the feasibility of storing 50+ million tonnes (Mt) of CO 2 . The results indicated CO 2 injection combined with ARM may enable permanent storage of 50+ Mt of CO 2 . The area of review (AOR), the area in which underground sources of drinking water (USDWs) might be endangered during CO 2 injection, was assessed for the simulation scenarios. In comparison to a case without ARM, brine extraction resulted in a much smaller AOR, covering an area of 42 square miles (108.8 km 2 ), roughly one-fourth the size of an AOR resulting from CO 2 injection without ARM. Our findings, presented in this paper, indicate that CO 2 injection with ARM can improve the CO 2 storage capacity of a geologic storage complex up to 100% while also reduce the rate of pressure buildup in the subsurface, resulting in a 75% reduction in AOR. This may help in lowering carbon capture and storage project costs, risks, and effort needed to meet monitoring requirements for a storage project.

54 ENVIRONMENTAL SCIENCES↗