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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Atomically Precise Graphene Nanoribbon Transistors with Long-Term Stability and Reliability

Atomically precise graphene nanoribbons (GNRs) synthesized from the bottom-up exhibit promising electronic properties for high-performance field-effect transistors (FETs). The feasibility of fabricating FETs with GNRs (GNRFETs) has been demonstrated, with ongoing efforts aimed at further improving their performance. However, their long-term stability and reliability remain unexplored, which is as important as their performance for practical applications. In this work, we fabricated short-channel FETs with nine-atom-wide armchair GNRs (9-AGNRFETs). We revealed that the on-state (/ ON ) current performance of the 9-AGNRFETs deteriorates significantly over consecutive full transistor on and off logic cycles, which has neither been demonstrated nor previously considered. To address this issue, we deposited a thin ~10 nm thick atomic layer deposition (ALD) layer of aluminum oxide (Al 2 O 3 ) directly on these devices. The integrity, compatibility, electrical performance, stability, and reliability, of the GNRFETs before and/or after Al 2 O 3 deposition were comprehensively studied. The results indicate that the observed decline in electrical device performance is most likely due to the degradation of contact resistance over multiple measurement cycles. We successfully demonstrated that the devices with the Al 2 O 3 layer operate well up to several thousand continuous full cycles without any degradation. Our study offers valuable insights into the stability and reliability of GNR transistors, which could facilitate their large-scale integration into practical applications.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Al-rich AlGaN high electron mobility transistor gate metallization study up to 600 °C in air

Here we report a comparative study of three rectifying gate metals, W, Pd, and Pt/Au, on ultrawide bandgap Al 0.86 Ga 0.14 N barrier/Al 0.7 Ga 0.3 N channel high electron mobility transistors for use in extreme temperatures. The transistors were electrically characterized from 30 to 600 °C in air. Of the three gate metals, the Pt/Au stack exhibited the smallest change in threshold voltage (0.15 V, or 9% change between the 30 and 600 °C values, and a maximum change of 42%), the highest on/off current ratio (1.5 × 10 6 ) at 600 °C, and a modest forward gate leakage current (0.39 mA/mm for a 3,V gate bias) at 600 °C. These favorable results showcase AlGaN channel high electron mobility transistors' ability to operate in extreme temperature environments.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Molybdenum Contacts to MoS 2 Field‐Effect Transistors: Schottky Barrier Extraction, Electrical Transport, and Low‐Frequency Noise

MoS 2 has great interest for nanoscale electronic devices, including transistors and sensors. Defect‐free structure, clean interface with the gate dielectric, and metals with suitable metal–semiconductor junctions are key for reliable devices. Molybdenum is shown as an excellent electrode for MoS 2 field‐effect transistors (FETs), but the correlation among device current, field‐effect mobility, and the low‐frequency noise (LFN) with number of atomic layers is not studied. Furthermore, the impact of Mo/MoS 2 Schottky barrier on electronic injection and scattering in the device needs to be understood. Herein, by studying the FETs with channels of different numbers of atomic‐layer thicknesses, it is shown that a molybdenum metal contact to MoS 2 provides reliable current injection with low Schottky barrier height, low contact resistance, low electron–phonon scattering, and negligible impurity scattering. The mobility and LFN are optimal at a channel thickness of ≈12 atomic layers, which is consistent with the “mobility maximum window” in MoS 2 transistors with prior studies using other contact metals.

Kwon, Jiseok↗
DOE OSTI2020

Ultra‐Steep Slope Impact Ionization Transistors Based on Graphene/InAs Heterostructures

With the continued scaling of transistors, there is a growing trend for developing steep slope transistors with subthreshold swing (SS) below Boltzmann limitation ( k T/ q ). To this end, impact ionization metal oxide semiconductor (I‐MOS) transistors are attractive for a unique combination of high ON‐state current density, small hysteresis, and ultra‐steep SS slope. However, the performance of I‐MOS is generally limited by the relatively thick depletion region and large operation voltage required for the activation of impact ionization (typically >5 V). Herein, a high‐performance I‐MOS is constructed by van der Waals integrating single‐crystal InAs film with graphene. Due to the low bandgap of InAs as well as the semi‐metallic nature of graphene, the InAs/graphene I‐MOS demonstrates a low operation voltage of 1.5 V, high ON‐state current of 230 μA μm −1 , steep SS <0.6 mV dec −1 , and large ON–OFF ratio >10 6 at temperature below 200 K. Furthermore, a negative transconductance and steep current oscillation is observed in the subthreshold regime, and a device working mechanism is proposed for this novel phenomenon. This study not only pushes the performance limit of I‐MOS but also defines a general pathway to van der Waals heterostructures between conventional III–V compound semiconductors and novel 2D materials for unconventional device functions.

Liu, Yuan↗
DOE OSTI2026

Enhancing mobility and interface state engineering via UV-ozone treatment in BEOL-compatible ultrathin TiO 2 transistors

It has emerged as a potential candidate to improve the performance of monolithic-three-dimensional (M3D) integration of fused logic and memories through low-temperature in situ synthesis of high-performance metal–oxide–semiconductor (MOS) transistors. Here, we report the demonstration of the BEOL-compatible low thermal budget (350 °C) fabrication process of ultrathin-TiO2 transistors by the combination of RTA and UV-ozone treatment (RTA-UVOz). UV–ozone (UVOz) treatment of TiO2 anatase films significantly enhances stability, boosting ION current and field effect mobility (μ FE ) by two times of magnitude in TiO2 TFTs. UV ozone treatment helps to eliminate pre-existing oxygen vacancies and carbon contamination on TiO2 channels even at low temperature (100 °C), resulting in high-quality channel/dielectric interfaces with low interface states (D it ). During UVOz treatment, oxygen species (O x ) passivate the oxygen vacancies ($V$$^{2+}_{o}$), and hence low concentration of $V$$^{2+}_{o}$ would be left for ionization/de-ionization under PBS/NBS, leading to improved bias stress stability. Furthermore, the TiO 2 TFTs with thin ZrO 2 gate dielectric exhibited excellent performance including a lower subthreshold swing (SS) of 98 mV/dec with high drive I ON current ∼ 4.5 μA/μm, a high I ON /I OFF > 10 9 , and mobility μFE of 7 cm 2 /V-s under a battery powered voltage of 1 V. UV–ozone treatment enables high-performance, CMOS-compatible TiO 2 transistors with a low thermal budget, ideal for next-generation flexible, energy-efficient electronics.

BEOL↗
DOE OSTI2025

Thermally Stable Ruthenium Contact for Robust p‑Type Tellurium Transistors

Tellurium (Te) is attractive for p-channel transistors due to its high hole mobility. Despite having a low thermal budget suitable for back-end-of-line (BEOL) monolithic integration, the practical realization of Te transistors is hindered by its thermal stability. In this work, we investigate thermal stability for Te thin films grown via scalable thermal evaporation. Our findings identify ruthenium as a more thermally stable contact for p-type Te transistors, capable of withstanding temperatures up to 250 °C. Ruthenium exhibits significantly lower diffusivity in Te compared to other contact metals commonly used such as nickel and palladium. Using the transfer-length method, we measured a contact resistance of 1.25 kΩ·μm at the ruthenium-tellurium interface. Additionally, the incorporation of high-κ ZrO2 encapsulation not only suppresses the sublimation of the Te channel at elevated temperatures but also serves as the gate dielectric in top-gate devices operating at 1 V, achieving an on/off current ratio of 105.

Rahman, I K M Reaz↗
DOE OSTI2022

Highly stretchable organic electrochemical transistors with strain-resistant performance

Realizing fully stretchable electronic materials is central to advancing new types of mechanically agile and skin-integrable optoelectronic device technologies. Here we demonstrate a materials design concept combining an organic semiconductor film with a honeycomb porous structure with biaxially prestretched platform that enables high-performance organic electrochemical transistors with a charge transport stability over 30-140% tensional strain, limited only by metal contact fatigue. In this work, the prestretched honeycomb semiconductor channel of donor-acceptor polymer poly(2,5-bis(2-octyldodecyl)-3,6-di(thiophen-2-yl)-2,5-diketo-pyrrolopyrrole-alt-2,5-bis(3-triethyleneglycoloxy-thiophen-2-yl) exhibits high ion uptake and completely stable electrochemical and mechanical properties over 1,500 redox cycles with 10(4) stretching cycles under 30% strain. Invariant electrocardiogram recording cycles and synapse responses under varying strains, along with mechanical finite element analysis, underscore that the present stretchable organic electrochemical transistor design strategy is suitable for diverse applications requiring stable signal output under deformation with low power dissipation and mechanical robustness. Highly stretchable organic electrochemical transistors with stable charge transport under severe tensional strains are demonstrated using a honeycomb semiconducting polymer morphology, thereby enabling controllable signal output for diverse stretchable bioelectronic applications.

36 MATERIALS SCIENCE↗
DOE OSTI2019

Evaporated tellurium thin films for p-type field-effect transistors and circuits

There is an emerging need for semiconductors that can be processed at near ambient temperature with high mobility and device performance. Although multiple n-type options have been identified, the development of their p-type counterparts remains limited. In this paper, we report the realization of tellurium thin films through thermal evaporation at cryogenic temperatures for fabrication of high-performance wafer-scale p-type field-effect transistors. We achieve an effective hole mobility of ~35 cm 2 V –1 s –1 , on/off current ratio of ~10 4 and subthreshold swing of 108 mV dec –1 on an 8-nm-thick film. High-performance tellurium p-type field-effect transistors are fabricated on a wide range of substrates including glass and plastic, further demonstrating the broad applicability of this material. Significantly, three-dimensional circuits are demonstrated by integrating multi-layered transistors on a single chip using sequential lithography, deposition and lift-off processes. Finally, various functional logic gates and circuits are demonstrated.

42 ENGINEERING↗
DOE OSTI2022

Ultrathin ferroic HfO 2 –ZrO 2 superlattice gate stack for advanced transistors

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO 2 , which remains the material of choice to date. Here we report HfO 2 –ZrO 2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric–antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal–oxide–semiconductor capacitors is equivalent to an effective SiO 2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO 2 -based high-dielectric-constant gate stacks without scavenging the interfacial SiO 2 , which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO 2 –ZrO 2 multilayers, stabilized with competing ferroelectric–antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO 2 -based high-dielectric-constant materials.

36 MATERIALS SCIENCE↗
DOE OSTI2026

GaN Core-shell Nanofin Vertical Transistor (CoNVerT): A New Direction for Power Electronics (Final Scientific/Technical Report)

A novel power transistor architecture, the GaN c ore-shell n anofin ver tical transistor (CoNVerT) to address fundamental challenges in realizing the ultimate limit of GaN power transistor performance was explored experimentally. This technology promises ultra-high-efficiency high voltage/high power applications (e.g. DC/DC converters, motor control, fast charging, actuation), as well as to operate in harsh environments. The device exploits a vertical superjunction structure based on an experimentally-validated core-shell nanofin growth process in which lateral p-n heterojunctions are formed in a single growth step, while still maintaining vertical current flow for compact die size and low cost. The concept leverages the best properties of GaN for mid-range voltage applications: high mobility, high breakdown voltage, and native heterojunction enhancement-mode operation. Due to the crystallographic nature of the nanofin growth by molecular beam epitaxy, the sidewall heterojunctions occur on non-polar planes, resulting in ultra-smooth interfaces for high mobility, no sidewall etch damage and related surface/interface states, and elimination of piezoelectric effects that can limit reliability in conventional structures. This also facilitates superjunction formation for maximum device performance, and the selective-area growth of the nanofin results in dislocation-free growth, even on low-cost Si (111) substrate. In this program, core-shell nanofins were grown by molecular beam epitaxy, test structures to evaluate the doping, resistivity, and other electrical properties were fabricated, and the material and test structures were characterized in detail. The work identified clear potential (e.g., the doping was well controlled as required for superjunction concepts), but also additional areas that require additional effort to resolve (some unexpected crystal defects were encountered that require additional engineering to overcome). Simulation studies of the proposed concept validate that the fundamental approach is very promising, but additional effort in experimental realization is needed.

42 ENGINEERING↗
NASA NTRS1965

Transistor voltage comparator performs own sensing

Detection of the highest voltage input among a group of varying voltage inputs is accomplished by a transistorized voltage comparison circuit. The collector circuits of the transistors perform the sensing function. Input voltage levels are governed by the transistors.

Cliff, R. A.↗
NASA NTRS1965

Simple circuit reduces transistor switching time

Silicon-Controlled Rectifier /SCR/, gated by a voltage divider, controls the potentiometer in transistorized switching circuits. The SCR acts as a gate to trigger the switching transistor only when the input signal reaches an amplitude that will switch the transistor rapidly.

Source record↗
NASA NTRS1966

Improved chopper circuit uses parallel transistors

Parallel transistor chopper circuit operates with one transistor in the forward mode and the other in the inverse mode. By using this method, it acts as a single, symmetrical, bidirectional transistor, and reduces and stabilizes the offset voltage.

Source record↗
NASA NTRS1966

Metal Oxide Silicon /MOS/ transistors protected from destructive damage by wire

Loop of flexible, small diameter, nickel wire protects metal oxide silicon /MOS/ transistors from a damaging electrostatic potential. The wire is attached to a music-wire spring, slipped over the MOS transistor case, and released so the spring tensions the wire loop around all the transistor leads, shorting them together. This allows handling without danger of damage.

Deboo, G. J.↗
NASA NTRS1973

Coaxial inverted geometry transistor having buried emitter

The invention relates to an inverted geometry transistor wherein the emitter is buried within the substrate. The transistor can be fabricated as a part of a monolithic integrated circuit and is particularly suited for use in applications where it is desired to employ low actuating voltages. The transistor may employ the same doping levels in the collector and emitter, so these connections can be reversed.

Hruby, R. J.↗
NASA NTRS1976

Modeling of short channel MOS transistors

Higher frequency response in MOS technology can be obtained by shortening the channel length. One approach for doing this involves an employment of higher resolution lithography technology. A second approach makes use of a double-diffused MOS transistor (DMOS). It is pointed out that the ordinary method of modeling the transistors used in both approaches is not accurate. An investigation is conducted of the questions which have to be considered for DMOS modeling. The modeling of a short channel MOS transistor is discussed, taking into account the derivation of the threshold voltage equation. Excellent agreement between theoretical and experimental data shows the accuracy of the described modeling approach.

Lin, H. C.↗
NASA NTRS1979

High-Speed, high-power, switching transistor

Silicon transistor rate for 200 angstroms at 400 to 600 volts combines switching speed of transistors with ruggedness, power capacity of thyristor. Transistor introduces unique combination of increased power-handling capability, unusally low saturation and switching losses, and submicrosecond switching speeds. Potential applications include high power switching regulators, linear amplifiers, chopper controls for high frequency electrical vehicle drives, VLF transmitters, RF induction heaters, kitchen cooking ranges, and electronic scalpels for medical surgery.

Carnahan, D.↗
NASA NTRS1981

Fabrication and high temperature characteristics of ion-implanted GaAs bipolar transistors and ring-oscillators

Ion implantation techniques that permit the reproducible fabrication of bipolar GaAs integrated circuits are studied. A 15 stage ring oscillator and discrete transistor were characterized between 25 and 400 C. The current gain of the transistor was found to increase slightly with temperature. The diode leakage currents increase with an activation energy of approximately 1 eV and dominate the transistor leakage current 1 sub CEO above 200 C. Present devices fail catastrophically at about 400 C because of Au-metallization.

Doerbeck, F. H.↗