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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4

Continuous multimodal technologies in industrial microbiology: potential for achieving high process performance and agility

The field of industrial microbiology has great potential to tackle the most pressing challenges facing society, but today, this entails much more than classical fermentation technology followed by product upgrading. Methods are needed to confer unit-operation-level functionality and whole-system-level robustness, as well as flexibility. As examples of this concept, we focus here on methodologies often deployed at industrial scale as discrete processes—such as biological, chemical, and electrochemical unit operations—that are also capable of substantial complementarity when combined sequentially and operated continuously. A key and relatively new type of conversion step is made possible by catalyst immobilization methods at both the enzymatic and cellular level. Cases drawn from electro-fermentation for acetoin production and syngas-mediated microbial electrosynthesis of ethanol exemplify the synergy of combined operational approaches. Because modular processes can be treated as a series of reactor elements, considerable flexibility is possible. As discussed, however, not all processes are amenable to this intensification.

09 BIOMASS FUELS↗

Additive Manufacturing of Frequency-Agile W-Band Packaging

Abstract —In this paper we demonstrate a fully additively manufactured packaged W-band amplifier with integrated bypass capacitors. This package was fabricated using a chip-first approach and aerosol jet printing. Package substrates (dielectrics), conductors and interconnects are printed around a bare die attached to a carrier. This package uses shaped ramp interconnects, allowing for frequency agnostic package performance of the interconnect with no impedance discontinuity, within the physical limits of the printer. High dielectric constant thin films of a polymer-matrix nanocomposite for bypass capacitors were printed using multi-material aerosol jet printing. The maximum measured packaged gain is 14.9 dB in the W-band, compared to the maximum bare die gain of 15.5 dB in the same frequency range. From 75 - 92 GHz, the average package loss is 1.1 dB including 3 mm transmission line, interconnects, and a GSG launch structure correlating to an average loss of 0.37 dB/mm.

Additive manufacturing, aerosol jet printing, hete↗

SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators

Next generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized with both commercial and open source logic design flows. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimension

Minutoli, Marco↗

Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis

Domain-specific designs offer greater energy efficiency and performance gain than general-purpose processors. For this reason, modern system-on-chips have a significant portion of their silicon area with custom accelerators. However, designing hardware by hand is laborious and time-consuming, given the large design space and the performance, power, and area constraints that are not realized in the software. Moreover, domain-specific algorithms (e.g., machine learning models) are evolving quickly, challenging the accelerator design further. To address these issues, this paper presents SODA Synthesizer, an automated open-source high-level ML framework to Verilog modular compiler targeting AI/ML Application-Specific Integrated Circuits (ASICs) accelerators. SODA tightly couples the Multi- Level Intermediate Representation (MLIR) compiler infrastructure [24] and open-source HLS approaches. Thus, SODA can support various ML frameworks and algorithms and can perform optimizations that combine specialized architecture templates and conventional HLS to generate the hardware modules. In addition, SODA’s closed-loop design space exploration (DSE) engine allows developers to perform end-to-end design space explorations on different metrics and technology nodes.

Zhang, Jeff↗

OCTOKV: An Agile Network-Based Key-Value Storage System with Robust Load Orchestration

In this paper, we propose OctoKV, an innovative network-based key-value storage system. OctoKV addresses the repetitive address translation overhead associated with traditional key-value stores running on file systems on the client side. To mitigate this overhead, we implemented the key-value store on the server side using NVMe-oF and a user-level NVMe driver. In particular, we employed fine-grained resource monitoring and load balancing based on heuristics to optimize I/O performance. OctoKV is deployed on a Linux cluster with Intel SPDK. The extensive evaluation shows that OctoKV achieves lower I/O response times in comparison to traditional approaches where key-value stores run on the client side. Also, the proposed load balancing strategies efficiently enhance I/O response times by equally distributing the workload from overloaded cores to other cores.

Khan, Awais↗