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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2000

An Optical Bit-Counting Algorithm

This paper addresses the omnipresent problem of counting bits - an operation discussed since the very early stages of the establishing of computer science. The need for a quick bit-counting method acquires a special significance with the proliferation of search engines on the Internet. It arises in several other computer applications. This is especially true in information retrieval in which an array of binary vectors is used to represent a characteristic function (CF) of a set of qualified documents. The number of "I"s in the CF equals the cardinality of the set. The process of repeated evaluations of this cardinality is a pivotal point in choosing a rational strategy for deciding whether to constrain or broaden the search criteria to ensure selection of the desired items. Another need for bit-counting occurs when trying to determine the differences between given files, (images or text), in terms of the Hamming distance. An Exclusive OR operation applied to a pair of files results in a binary vector array of mismatches that must be counted.

Mack, Marilyn↗
NASA NTRS2002

Inadvertently programmed bits in Samsung 128 Mbit flash devices: a flaky investigation

JPL's X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM) board based on flash memories. The Samsung 128Mb device chosen was found to demonstrate bit errors (mostly program disturbs) and block-erase failures that increase with cycling. Low temperature, certain pseudo- random patterns, and, probably, higher bias increase the observable bit errors. An experiment was conducted to determine the wearout dependence of the bit errors to 100k cycles at cold temperature using flight-lot devices (some pre-irradiated). The results show an exponential growth rate, a wide part-to-part variation, and some annealing behavior.

flash memory program disturb wearout erase fail re↗
DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗
NASA NTRS1965

Drill bit design assures clean holes in laminated materials

Drill bit eliminates delamination when drilling laminated material. It cuts or shaves the material as it progresses through it. The bit acts to hold down the material during drilling to prevent tearing or ripping and produces a clean, smooth and defect-free hole. It prevents chipping in stretched plastic windows for high-altitude, high-performance aircraft.

Tillotson, R. N.↗
NASA NTRS1974

Synthesis and evaluation of phase detectors for active bit synchronizers

Self-synchronizing digital data communication systems usually use active or phase-locked loop (PLL) bit synchronizers. The three main elements of PLL synchronizers are the phase detector, loop filter, and the voltage controlled oscillator. Of these three elements, phase detector synthesis is the main source of difficulty, particularly when the received signals are demodulated square-wave signals. A phase detector synthesis technique is reviewed that provides a physically realizable design for bit synchronizer phase detectors. The development is based upon nonlinear recursive estimation methods. The phase detector portion of the algorithm is isolated and analyzed.

Mcbride, A. L.↗
NASA NTRS1976

A 128K-bit CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications.

Siemens, K. H.↗
NASA NTRS1975

Performance of a finite phase state bit-synchronization loop with and without sequential filters

A discrete phase state bit-synchronization loop is proposed for synchronization and detection of a binary nonreturn-to-zero (NRZ) process. The general loop model is developed for 11 and 17 phase states with optional sequential loop filter. Loop performance is considered in terms of the phase error density function, rms phase error, and mean time to bit slippage. It is shown that satisfactory loop performance can be achieved at -3 dB SNR through use of sequential loop filters.

Ransom, J. J.↗
NASA NTRS1977

Measurement of bit-error rate

Error rate of RF digital communication link is measured at low signal-to-noise ratios using this technique. In this method, identical pseudo-random sequences of pulses are generated at transmitter and receiver of link. However, comparison of two sequences at receiver involves integration that makes bit-tracking threshold depend on length of pseudo-random sequence, rather than on actual rate of transmission of individual bits.

Fowler, J.↗
NASA NTRS1976

Bit error rate measurement for evaluation of a fiber optic link

Digital fiber-optic data-link terminal modules are being developed in a number of laboratories, and often the modules take the form of black boxes without convenient access to internal signals. This paper discusses types of measurements which can be made using only the digital terminals of the link. Bit-error-rate (BER) vs signal-power data can, of course, provide a means for proving overall link performance, but it can also be used to determine certain internal parameters of the receiver. The theoretical dependence of the BER-vs-light-signal-power curve shape on receiver input-noise equivalent power and comparator slicing level is discussed. BER-vs-light-signal-power measurements obtained with an experimental link are presented and interpreted with the aid of the theoretical curves. The effects of other problems, such as hum or oscillation, on the BER data are mentioned. Sensitivity of the system BER to bit rate is also discussed, with application to determining system operating limits. Since BER measurements are simple to make and can easily be automated, they may prove to be a useful means for either laboratory evaluation or production-line acceptance testing of sealed terminal modules.

Bergman, L. A.↗
NASA NTRS1976

120 MB/S and 240 MB/S bit synchronizer-signal conditioners for NASA high data rate applications

Two bit synchronizer-signal conditioners (BSSC) developed for NASA high data rate applications such as earth resources monitoring are described. One BSSC is centered at 120 MB/s and the other at 240 Mb/s. These subsystems are featured out of the total hardware developed because the BSSC is such a key subsystem in determining overall system statistical performance. These units represent an evolution of high data rate BSSC's available at low data rates. Numerous inputs/outputs, control functions, indicators, plus the ability to minimize the effects of various signal perturbations are provided. Examples of allowed perturbations are input level variations, bit rate variance static and dynamic, baseline, transition density, bandlimiting, etc., as well as noise. Emphasis in the past has been primarily concerned only with noise.

Gray, J. S.↗
NASA NTRS1978

Preliminary design for a standard 10 sup 7 bit Solid State Memory (SSM)

A modular concept with three separate modules roughly separating bubble domain technology, control logic technology, and power supply technology was employed. These modules were respectively the standard memory module (SMM), the data control unit (DCU), and power supply module (PSM). The storage medium was provided by bubble domain chips organized into memory cells. These cells and the circuitry for parallel data access to the cells make up the SMM. The DCU provides a flexible serial data interface to the SMM. The PSM provides adequate power to enable one DCU and one SMM to operate simultaneously at the maximum data rate. The SSM was designed to handle asynchronous data rates from dc to 1.024 Mbs with a bit error rate less than 1 error in 10 to the eight power bits. Two versions of the SSM, a serial data memory and a dual parallel data memory were specified using the standard modules. The SSM specification includes requirements for radiation hardness, temperature and mechanical environments, dc magnetic field emission and susceptibility, electromagnetic compatibility, and reliability.

Hayes, P. J.↗
NASA NTRS1979

Multiple speed expandable bit synchronizer

A multiple speed bit synchronizer was designed for installation in an inertial navigation system data decoder to extract non-return-to-zero level data and clock signal from biphase level data. The circuit automatically senses one of four pre-determined biphase data rates and synchronizes the proper clock rate to the data. Through a simple expansion of the basic design, synchronization of more than four binarily related data rates can be accomplished. The design provides an easily adaptable, low cost, low power alternative to external bit synchronizers with additional savings in size and weight.

Bundinger, J. M.↗
NASA NTRS1977

Bit timing with pulse distortion and intersymbol interference

Pulse distortion and intersymbol interference due to insufficient filtering in PCM and PSK channels cause performance degradation in terms of both bit error probabilities and timing errors. This paper reports the results of a study analyzing these effects on bit timing subsystems. Consideration is given to both the filter-rectifier and transition tracking type of timing subsystem. Although both these systems perform similarly in high SNR and ideal pulse models, pulse distortion and intersymbol affects each differently. The primary effects in both systems is to cause the presence of an irreducible mean squared timing error due to the intersymbol which limits the ultimate performance. Design procedures to minimize the anomalies of both systems are presented, and indicate modifications of the standard timing subsystems. It is found that specific design directions depend on whether the intersymbol or the receiver noise tends to dominate.

Gagliardi, R. M.↗
NASA NTRS1981

Simulation and studies of spaceborne synthetic aperture radar image quality with reduced bit rate

A computer simulation program that is used to study the effects of digitization in spaceborne synthetic aperture radar systems is described. An analytical study of the distortion noise introduced by the digitization process at various gain settings, sampling rates and bit error rates is presented and the results agree well with those obtained from the simulation program. The simulation program is also used to study the spatial frequency response of hard-limiting (quantizing to 1-bit) synthetic aperture radar systems. The implications of these results on synthetic aperture radar system design are discussed.

Li, F.↗
NASA NTRS1982

High density bit transition requirements versus the effects on BCH error correcting code

The design to achieve the required bit transition density for the Space Shuttle high rate multiplexes (HRM) data stream of the Space Laboratory Vehicle is reviewed. It contained a recommended circuit approach, specified the pseudo random (PN) sequence to be used and detailed the properties of the sequence. Calculations showing the probability of failing to meet the required transition density were included. A computer simulation of the data stream and PN cover sequence was provided. All worst case situations were simulated and the bit transition density exceeded that required. The Preliminary Design Review and the critical Design Review are documented. The Cover Sequence Generator (CSG) Encoder/Decoder design was constructed and demonstrated. The demonstrations were successful. All HRM and HRDM units incorporate the CSG encoder or CSG decoder as appropriate.

Ingels, F. M.↗
NASA NTRS1984

New Short Constraint Length, Rate 1/N Convolutional Codes which Minimize Required E Sub B/n Sub o for Given Bit Error Rate

Instead of using the criterion of maximum free distance, (df) or the maximum (df) with minimizing a few first distance profiles, short constraint length rate 1/N convolution codes were searched using a criterion of minimizing required bit energy-to-noise density ratio, E(b)/N(o), for a given value of desired bit error rate (BER), for the goodness of a code. The considered channel was binary antipodal signaling over additive white Gaussian noise and no quantization at the channel output. For the BER calculations, the transfer function bounding technique was used. Partial searches were performed using some known facts and a very useful idea that "good codes generate good codes.'' That is, for a given constraint length K, good rate 1/(N + 1) codes can be found by extending the code generator matrices of good rate 1/N codes. The code search results are tabulated for 3 or = K or = 7 and 2 or = N or = 8. For many pairs of K and N, the new codes are shown to save 0.1 to 0.4 dB in the required E(b)/N(o) compared to previously reported codes. Additionally, the benefits of coding bandwidth expansion are confirmed with the new codes.

Lee, P. J.↗