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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1973

A centre for accommodative vergence motor control

Latencies in accommodation, accommodative-vergence, and pupil-diameter responses to changing accommodation stimuli, as well as latencies in pupil response to light-intensity changes were measured. From the information obtained, a block diagram has been derived that uses the least number of blocks for representing the accommodation, accommodative-vergence, and pupil systems. The signal transmission delays over the various circuits of the model have been determined and compared to known experimental physiological-delay data. The results suggest the existence of a motor center that controls the accommodative vergence and is completely independent of the accommodation system.

Wilson, D.↗
NASA NTRS1988

Comparison of electrically driven lasers for space power transmission

High-power lasers in space could provide power for a variety of future missions such as spacecraft electric power requirements and laser propulsion. This study investigates four electrically pumped laser systems, all scaled to 1-MW laser output, that could provide power to spacecraft. The four laser systems are krypton fluoride, copper vapor, laser diode array, and carbon dioxide. Each system was powered by a large solar photovoltaic array which, in turn, provided power for the appropriate laser power conditioning subsystem. Each system was block-diagrammed, and the power and efficiency were found for each subsystem block component. The copper vapor system had the lowest system efficiency (6 percent). The CO2 laser was found to be the most readily scalable but has the disadvantage of long laser wavelength.

Deyoung, R. J.↗
NASA NTRS1981

Verification of the Space Shuttle entry GN&C system

The certification procedures for the initial Shuttle flight are discussed. Particular attention is paid to the entry guidance, navigation, and control (GNC) verification, comprising tests, analysis, demonstration, inspection, and simulation. Flow diagrams for the verification and operational flight sequences are provided, along with a block diagram of the GNC circuitry interfaces. The development of the test matrix software for the GNC is outlined, noting the constant interplay between software verification and spacecraft reconfiguration to meet simulated performance requirements. Comparison of GNC performance predictions with actual entry flight data showed a good match in all performance areas except for sideslip excursions, bank overshoots, an area of transonic buffet, and an increased lift/drag ratio in the preflare to landing flight phase.

Van Hoften, J. D. A.↗
NASA NTRS1972

SYSTID - A flexible tool for the analysis of communication systems.

Description of the System Time Domain Simulation (SYSTID) computer-aided analysis program which is specifically structured for communication systems analysis. The SYSTID program is user oriented so that very little knowledge of computer techniques and very little programming ability are required for proper application. The program is designed so that the user can go from a system block diagram to an accurate simulation by simply programming a single English language statement for each block in the system. The mathematical and functional models available in the SYSTID library are presented. An example problem is given which illustrates the ease of modeling communication systems. Examples of the outputs available are presented, and proposed improvements are summarized.

Dawson, C. T.↗
NASA NTRS2022

Run Time Assurance for Electric Vertical Takeoff and Landing Aircraft

NASA is conducting research to demonstrate and evaluate the application of Run Time Assurance (RTA) as a means to assure safety in Electric Vertical Takeoff and Landing (eVTOL) aircraft with highly automated or autonomous flight capability supervised by a single onboard pilot. The work described in this report demonstrates an application of RTA and examines the implications for design and analysis of aircraft functions and systems; aircraft safety hazards; safety assurance; development assurance; and pilot tasks and performance. This research effort also seeks to assess the efficacy of the combined application of traditional Functional Hazard Analysis (FHA) and the more modern System Theoretic Process Analysis (STPA) techniques to perform hazard analyses on aircraft with complex automated and autonomous systems and an onboard pilot. During the research effort we developed architectural designs of two alternate eVTOL aircraft, generally following the process characterized in the SAE standards ARP4754 and ARP4761. The design has focused on the control architectures of these aircraft, which are identical except that one incorporates RTA techniques to reduce the criticality of some key software components. Artifacts of this process include a taxonomy of aircraft-level functions, aircraft-level architecture diagrams, aircraft-level functional hazard assessments (AFHA), function allocations onto aircraft systems and subsystems, functional block diagrams for a select set of control-related functions, and system-level functional hazard assessments (SFHA) for those functions. This project has highlighted the notion that DAL D is something of a sweet spot for low-confidence controllers in an RTA-based design. Among the many activities described in DO-178C, the activities related to requirement verifiability, algorithmic accuracy, and test coverage can be the most challenging for the kinds of advanced control techniques that may be desirable in novel UAM designs, such as adaptive control, machine-learning, artificial intelligence, numerical search, and Monte Carlo based algorithms. Moreover, the standard requires that development teams demonstrate that errors leading to unacceptable failure conditions have been removed from the software. The RTA architecture, which cordons off the low-confidence function, makes it much easier to show this for these kinds of algorithms. With regard to the use of STPA and FHA as complementary hazard analysis techniques, our research effort led us to the conclusion that STPA should be used to derive requirements for hardware and software systems and/or components. Also, STPA is a natural complement to other processes in ARP4754A involving design studies and iteration.

Run-time assurance↗
NASA NTRS1976

Si/Li/ X-ray astronomical spectroscopy

The principles of operation of solid state nondispersive spectrometers are reviewed. Si(Li) is shown to be the preferred nondispersive X-ray spectrometer because of its inherent resolution advantages and its adaptability to the constraints and philosophy of the HEAO-B observatory. A schematic diagram is presented of the geometry of the HEAO-B solid state detector assembly as a block diagram of the primary logic mode of the HEAO-B X-ray spectrometer.

Holt, S. S.↗
NASA NTRS1990

Balloon-borne Infrared Telescope (BIRT) for far-infrared spectroscopy

The Japanese-made Balloon-borne Infrared Telescope (BIRT) designed for FIR astronomy is described. The BIRT system includes a 50-cm-diam telescope; an attitude-control system consisting of an attitude stabilization and a pointing and tracking subsystems; the ground support system consisting of four personal-computer systems; and electronics consisting of three small computer systems, servo circuits, power amplifiers, and other small circuits. Between 1985 and 1988, the BIRT has flown eight times, demonstrating that it is able to provide a suitable telescope observations on a stable platform with a long integration time. Structural diagrams of the BIRT overall system, the optical system, and the wobbling mechanism are presented along with a block diagram of the on-board electronics.

Shibai, Hiroshi↗
NASA NTRS2007

The JPL Cryogenic Dilatometer: Measuring the Thermal Expansion Coefficient of Aerospace Materials

This slide presentation details the cryogenic dilatometer, which is used by JPL to measure the thermal expansion coefficient of materials used in Aerospace. Included is a system diagram, a picture of the dilatometer chamber and the laser source, a description of the laser source, pictures of the interferometer, block diagrams of the electronics and software and a picture of the electronics, and software. Also there is a brief review of the accurace.error budget. The materials tested are also described, and the results are shown in strain curves, JPL measured strain fits are described, and the coefficient of thermal expansion (CTE) is also shown for the materials tested.

dilatometer↗
NASA NTRS1991

ETARA PC version 3.3 user's guide: Reliability, availability, maintainability simulation model

A user's manual describing an interactive, menu-driven, personal computer based Monte Carlo reliability, availability, and maintainability simulation program called event time availability reliability (ETARA) is discussed. Given a reliability block diagram representation of a system, ETARA simulates the behavior of the system over a specified period of time using Monte Carlo methods to generate block failure and repair intervals as a function of exponential and/or Weibull distributions. Availability parameters such as equivalent availability, state availability (percentage of time as a particular output state capability), continuous state duration and number of state occurrences can be calculated. Initial spares allotment and spares replenishment on a resupply cycle can be simulated. The number of block failures are tabulated both individually and by block type, as well as total downtime, repair time, and time waiting for spares. Also, maintenance man-hours per year and system reliability, with or without repair, at or above a particular output capability can be calculated over a cumulative period of time or at specific points in time.

Hoffman, David J.↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1973

Diagnostics of sources of disturbances and distribution of vibrations over the width of a tape in tape-feed mechanisms

Disturbances created by certain assemblies and components of tape-feed mechanisms (TFM) and acting on a moving magnetic tape are studied. The method, based on elements of digital logic, is established by stress-strain diagrams of the longitudinal deformations and vibrations across the width of a magnetic tape. Experimental studies were carried out for determination of the functional relationships of longitudinal deformations in a section of magnetic tape to the magnitude of roller play, tension vibrations rate of movement, and elasticity of magnetic tapes. A block diagram of the measurements is shown. Appropriate digital computer algorithms and programs were proposed for statistical analysis of the data obtained. Estimates of the mathematical expectation, dispersion, intercorrelation function, energy spectral density, and distribution pattern of the random process values were calculated.

Kenstavichyus, A. B. B.↗
NASA NTRS1975

Networks systems and operations

The application of wideband communication techniques for data links with satellites is discussed. A diagram of the demand assigned voice communications system is provided. The development of prototype integrated spacecraft paramps at S- and C-bands is described and the performance of space-qualified paramps is tabulated. The characteristics of a dual parabolic cylinder monopulse zoom antenna for use with the tracking and data relay satellite system (TDRSS) are analyzed. The development of a universally applicable transponder at S-band is reported. A block diagram of the major subassemblies of the S-band transponder is included. The technology aspects of network timing and synchronization of communication systems are to show the use of the Omega navigation system. The telemetry data compression system used during the Skylab program is evaluated.

Source record↗
NASA NTRS2004

Downlink Data Multiplexer

A multiplexer/demultiplexer system has been developed to enable the transmission, over a single channel, of four data streams generated by a variety of sources at different (including variable) bit rates. In the original intended application, replicas of this multiplexer/demultiplexer system would be incorporated into the spacecraft-to-ground communication systems of the space shuttles. The multiplexer of each system would be installed in the spacecraft, where it would acquire and process data from such sources as commercial digital camcorders, video tape recorders, and the spacecraft telemetry system. The demultiplexer of each system would be installed in a ground station. Purely terrestrial systems of similar design could be attractive for use in situations in which there are requirements to transmit multiple streams of high-quality video data and possibly other data over single channels. The figure is a block diagram of the multiplexer as configured to process data received via three fiber-optic channels like those of the International Space Station and one electrical-cable channel that conforms to the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard. (This standard consists of specifications of a high-speed serial data interface, the physical layer of which includes a cable known in the art as "FireWire." An IEEE 1394 interface can also transfer power between the components to which it is connected.) The fiber-optic channels carry packet and/or bit-stream signals that conform to the standards of the Consultative Committee for Space Data Systems (CCSDS). The IEEE 1394 interface accepts an isochronous signal like that from a digital camcorder or a video tape recorder. The processing of the four input data streams to combine them into one output stream is governed by a statistical multiplexing algorithm that features a flow-control capability and makes it possible to utilize the transmission channel with nearly 100-percent efficiency. This algorithm allocates the available bandwidth of the transmission channel to the data streams according to a combination of data rates and preassigned priorities. Incoming data streams that demand too much bandwidth are blocked. Bandwidth not needed for a transmission of a given data stream is allocated to other streams as available. Priority is given to the IEEE 1394 stream. In addition to the four incoming data streams, the multiplexer transmits data on the status of the system. An operator can monitor and control the multiplexer via displays and controls on the multiplexer housing. The output of the multiplexer is connected via a coaxial cable with an impedance of 50 Ohms to an interface circuit compatible with the space-shuttle high-speed digital downlink, which operates at a rate of 48 Mb/s.

Holland, Douglas↗
DOE OSTI2023

Reliability modeling in a predictive maintenance context: A margin-based approach

Current system reliability methods (typically based on fault trees or reliability block diagrams) can effectively propagate reliability data from the asset to the system level in order to identify system critical points. However, employed asset reliability data are an approximated integral representation of the past industrywide operational experience, and they neglect the present asset health status (available, for example, from online monitoring data and diagnostic assessments) and forecasted health projection (when available from prognostic models). Asset health should be informed solely by that specific asset’s current and historical performance data and should not be an approximated integral representation of the past industrywide operational experience (as currently performed by system reliability models through Bayesian updating processes). Sensor data, diagnostic assessments, and prognostic assessments are in fact not considered in plant reliability models used to inform system engineers on the most critical assets. In addition, the propagation of quantitative health data from the asset to the system level is a challenge given the diverse nature and structure of health data elements (e.g., vibration spectra, temperature readings, expected failure time). Ideally, in a predictive maintenance context, system reliability models should support decision making by propagating available health information from the asset to the system level in order to provide a quantitative snapshot of system health and identify the most critical assets. Here, this paper is directly addressing these two goals by proposing a different approach for reliability modeling that relies on asset diagnostic and prognostic assessments, along with monitoring data to measure asset health. The propagation of health data from the asset to the system level is performed through fault tree models not in probability terms, but in terms of margin where margin is the “distance” between the present status and an undesired event (e.g., failure or unacceptable performance). Through a cause-effect lens, while classical reliability models target the effect associated with asset performance, a margin-based approach focuses on the cause of an undesired asset performance (i.e., its health). Hence, thinking of reliability in terms of margins implies decision-making based on causal reasoning. We will show how fault tree models can be solved using a margin language and how this process can effectively assist system engineers to identify the most critical assets.

97 - MATHEMATICS AND COMPUTING↗