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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Balloon-borne Infrared Telescope (BIRT) for far-infrared spectroscopy

The Japanese-made Balloon-borne Infrared Telescope (BIRT) designed for FIR astronomy is described. The BIRT system includes a 50-cm-diam telescope; an attitude-control system consisting of an attitude stabilization and a pointing and tracking subsystems; the ground support system consisting of four personal-computer systems; and electronics consisting of three small computer systems, servo circuits, power amplifiers, and other small circuits. Between 1985 and 1988, the BIRT has flown eight times, demonstrating that it is able to provide a suitable telescope observations on a stable platform with a long integration time. Structural diagrams of the BIRT overall system, the optical system, and the wobbling mechanism are presented along with a block diagram of the on-board electronics.

Shibai, Hiroshi↗
NASA NTRS2007

The JPL Cryogenic Dilatometer: Measuring the Thermal Expansion Coefficient of Aerospace Materials

This slide presentation details the cryogenic dilatometer, which is used by JPL to measure the thermal expansion coefficient of materials used in Aerospace. Included is a system diagram, a picture of the dilatometer chamber and the laser source, a description of the laser source, pictures of the interferometer, block diagrams of the electronics and software and a picture of the electronics, and software. Also there is a brief review of the accurace.error budget. The materials tested are also described, and the results are shown in strain curves, JPL measured strain fits are described, and the coefficient of thermal expansion (CTE) is also shown for the materials tested.

dilatometer↗
NASA NTRS1991

ETARA PC version 3.3 user's guide: Reliability, availability, maintainability simulation model

A user's manual describing an interactive, menu-driven, personal computer based Monte Carlo reliability, availability, and maintainability simulation program called event time availability reliability (ETARA) is discussed. Given a reliability block diagram representation of a system, ETARA simulates the behavior of the system over a specified period of time using Monte Carlo methods to generate block failure and repair intervals as a function of exponential and/or Weibull distributions. Availability parameters such as equivalent availability, state availability (percentage of time as a particular output state capability), continuous state duration and number of state occurrences can be calculated. Initial spares allotment and spares replenishment on a resupply cycle can be simulated. The number of block failures are tabulated both individually and by block type, as well as total downtime, repair time, and time waiting for spares. Also, maintenance man-hours per year and system reliability, with or without repair, at or above a particular output capability can be calculated over a cumulative period of time or at specific points in time.

Hoffman, David J.↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1973

Diagnostics of sources of disturbances and distribution of vibrations over the width of a tape in tape-feed mechanisms

Disturbances created by certain assemblies and components of tape-feed mechanisms (TFM) and acting on a moving magnetic tape are studied. The method, based on elements of digital logic, is established by stress-strain diagrams of the longitudinal deformations and vibrations across the width of a magnetic tape. Experimental studies were carried out for determination of the functional relationships of longitudinal deformations in a section of magnetic tape to the magnitude of roller play, tension vibrations rate of movement, and elasticity of magnetic tapes. A block diagram of the measurements is shown. Appropriate digital computer algorithms and programs were proposed for statistical analysis of the data obtained. Estimates of the mathematical expectation, dispersion, intercorrelation function, energy spectral density, and distribution pattern of the random process values were calculated.

Kenstavichyus, A. B. B.↗
NASA NTRS1975

Networks systems and operations

The application of wideband communication techniques for data links with satellites is discussed. A diagram of the demand assigned voice communications system is provided. The development of prototype integrated spacecraft paramps at S- and C-bands is described and the performance of space-qualified paramps is tabulated. The characteristics of a dual parabolic cylinder monopulse zoom antenna for use with the tracking and data relay satellite system (TDRSS) are analyzed. The development of a universally applicable transponder at S-band is reported. A block diagram of the major subassemblies of the S-band transponder is included. The technology aspects of network timing and synchronization of communication systems are to show the use of the Omega navigation system. The telemetry data compression system used during the Skylab program is evaluated.

Source record↗
NASA NTRS2004

Downlink Data Multiplexer

A multiplexer/demultiplexer system has been developed to enable the transmission, over a single channel, of four data streams generated by a variety of sources at different (including variable) bit rates. In the original intended application, replicas of this multiplexer/demultiplexer system would be incorporated into the spacecraft-to-ground communication systems of the space shuttles. The multiplexer of each system would be installed in the spacecraft, where it would acquire and process data from such sources as commercial digital camcorders, video tape recorders, and the spacecraft telemetry system. The demultiplexer of each system would be installed in a ground station. Purely terrestrial systems of similar design could be attractive for use in situations in which there are requirements to transmit multiple streams of high-quality video data and possibly other data over single channels. The figure is a block diagram of the multiplexer as configured to process data received via three fiber-optic channels like those of the International Space Station and one electrical-cable channel that conforms to the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard. (This standard consists of specifications of a high-speed serial data interface, the physical layer of which includes a cable known in the art as "FireWire." An IEEE 1394 interface can also transfer power between the components to which it is connected.) The fiber-optic channels carry packet and/or bit-stream signals that conform to the standards of the Consultative Committee for Space Data Systems (CCSDS). The IEEE 1394 interface accepts an isochronous signal like that from a digital camcorder or a video tape recorder. The processing of the four input data streams to combine them into one output stream is governed by a statistical multiplexing algorithm that features a flow-control capability and makes it possible to utilize the transmission channel with nearly 100-percent efficiency. This algorithm allocates the available bandwidth of the transmission channel to the data streams according to a combination of data rates and preassigned priorities. Incoming data streams that demand too much bandwidth are blocked. Bandwidth not needed for a transmission of a given data stream is allocated to other streams as available. Priority is given to the IEEE 1394 stream. In addition to the four incoming data streams, the multiplexer transmits data on the status of the system. An operator can monitor and control the multiplexer via displays and controls on the multiplexer housing. The output of the multiplexer is connected via a coaxial cable with an impedance of 50 Ohms to an interface circuit compatible with the space-shuttle high-speed digital downlink, which operates at a rate of 48 Mb/s.

Holland, Douglas↗
NASA NTRS1966

Automated drafting system uses computer techniques

Automated drafting system produces schematic and block diagrams from the design engineers freehand sketches. This system codes conventional drafting symbols and their coordinate locations on standard size drawings for entry on tapes that are used to drive a high speed photocomposition machine.

Millenson, D. H.↗
NASA NTRS1969

Design and sparing techniques to meet specified performance life

Specified performance life technique starts with the general description of what is wanted, defines in block diagram the operational needs, and then defines the functional systems required. The technique is similar to a truncated reliability model, but the calculation is simplified by use of a Poisson distribution approach to failure probability.

Holstead, A. J., Jr.↗
NASA NTRS1970

Digital simulation program improved

Modified Integration Digital Analog Simulation /MIDAS/ program, which provides time oriented solutions to equations from system block diagram descriptions, is given greater speed, accuracy, flexibility, and applicability. Improved program incorporates additional elements for extended solution capability not readily available from analog computers.

Bramblett, E. K.↗
NASA NTRS1971

Multiple-mission telemetry

Progress report, block diagrams, and processing of multiple-mission telemetry of Deep Space Instrumentation Facility

Frey, W.↗
NASA NTRS1972

New detection method for rolling element and bearing defects

Instrument for detecting defects in rolling elements of bearings is described. Detection depends on rate at which rolling elements impact defect and establishes envelope amplitude of ball resonant frequency. Block diagram of instrument is provided and results obtained in conducting tests are reported.

Burchill, R. F.↗