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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

Senescence chips for ultrahigh-throughput isolation and removal of senescent cells

Cellular senescence plays an important role in organismal aging and age-related diseases. However, it is challenging to isolate low numbers of senescent cells from small volumes of biofluids for downstream analysis. Furthermore, there is no technology that could selectively remove senescent cells in a high-throughput manner. In this work, we developed a novel microfluidic chip platform, termed senescence chip, for ultrahigh-throughput isolation and removal of senescent cells. The core component of our senescence chip is a slanted and tunable 3D micropillar array with a variety of shutters in the vertical direction for rapid cell sieving, taking advantage of the characteristic cell size increase during cellular senescence. The 3D configuration achieves high throughput, high recovery rate, and device robustness with minimum clogging. We demonstrated proof-of-principle applications in isolation and enumeration of senescent mesenchymal stem cells (MSCs) from undiluted human whole blood, and senescent cells from mouse bone marrow after total body irradiation, with the single cell resolution. After scale-up to a multilayer and multichannel structure, our senescence chip achieved ultrahigh-throughput removal of senescent cells from human whole blood with an efficiency of over 70% at a flow rate of 300 ml/hr. Sensitivity and specificity of our senescence chips could be augmented with implementation of multiscale size separation, and identification of background white blood cells using their cell surface markers such as CD45. With the advantages of high throughput, robustness, and simplicity, our senescence chips may find wide applications and contribute to diagnosis and therapeutic targeting of cellular senescence.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2026

Directional dependence of equilibrated TLD-400 chips in multiple radiation fields

Fielding of thermoluminescent dosimeters (TLDs) for measurement of photon radiation dose in experiments is the standard practice for γ-irradiation facilities, pulsed power x-ray facilities, and reactor facilities at Sandia National Laboratories (SNL). Due to the high-dose experimental conditions and the mixed ( 1 n, γ) fields in these facilities, SNL radiation metrologists have historically used CaF 2 :Mn TLDs (also known as TLD-400). Recent inquiries to the radiation metrology staff have raised concerns that the aluminum-equilibrated TLD-400 chips may exhibit a directionally dependent response. The metrologists were asked whether the dose measured by the chip may be impacted by the angle of incidence on the equilibrated TLD. To provide a thorough answer to this query, a set of adjoint Monte Carlo radiation transport calculations was performed for three different equilibrated TLDs as well as bare TLD chips using the Integrated Tiger Series (ITS) code. The key feature of the adjoint calculations performed in this study is that each photon escaping the modeled geometry was tallied into angular bins to provide information on both the energy and angular dependence of the equilibrated chip. After the adjoint Monte Carlo calculations were completed, the resulting energy-dependent response function for each angular bin was convolved with multiple photon energy spectra representing various radiation facilities at SNL. The radiation facilities selected for analysis span a range of photon energies from approximately 1 keV up to approximately 20 MeV. Thus, the presented results are applicable to a wide variety of radiation facilities around the world. Although the bare TLD-400 chip was expected to display the largest variation due to the photon angle of impact on the dosimeter, the dosimeter with the thinnest aluminum equilibrator (SNL thin equilibrated TLD-400) was determined to have the biggest differential between the impact angle with the maximum dose ( D max ) and the impact angle with the minimum dose ( D min ). However, the SNL normal equilibrated TLD-400 chip demonstrated a dramatic reduction in that differential between maximum and minimum dose angles. The reduction in this differential is one of the dominant factors in experimenters’ choice to field these dosimeters at SNL radiation facilities. The results from the PNNL (Hanford) energy-flattening field capsule are consistent with the previous publications. The differential dose responses due to the photon impact angle indicate that experimenters should strive to field their TLD-400 dosimeters in a consistent manner to avoid additional uncertainty in the measurements based on dosimeter orientation.

Adjoint radiation transport↗
DOE OSTI2015

Method of mechanical holding of cantilever chip for tip-scan high-speed atomic force microscope

In tip-scan atomic force microscopy (AFM) that scans a cantilever chip in the three dimensions, the chip body is held on the Z-scanner with a holder. However, this holding is not easy for high-speed (HS) AFM because the holder that should have a small mass has to be able to clamp the cantilever chip firmly without deteriorating the Z-scanner’s fast performance, and because repeated exchange of cantilever chips should not damage the Z-scanner. This is one of the reasons that tip-scan HS-AFM has not been established, despite its advantages over sample stage-scan HS-AFM. Here, we present a novel method of cantilever chip holding which meets all conditions required for tip-scan HS-AFM. The superior performance of this novel chip holding mechanism is demonstrated by imaging of the α{sub 3}β{sub 3} subcomplex of F{sub 1}-ATPase in dynamic action at ∼7 frames/s.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Atom-resolved imaging with a silicon tip integrated into an on-chip scanning tunneling microscope

Limited throughput is a shortcoming of the Scanning Tunneling Microscope (STM), particularly when used for atomically precise lithography. To address this issue, we have developed an on-chip STM based on Microelectromechanical-Systems (MEMS) technology. The device reported here has one degree of freedom, replacing the Z axis in a conventional STM. The small footprint of the on-chip STM provides a great opportunity to increase STM throughput by incorporating a number of on-chip STMs in an array to realize parallel STM. The tip methodology adopted for the on-chip STM presented here, which is a batch-fabricated Si tip, makes our design conducive to this goal. In this work, we investigate the capability of this on-chip STM with an integrated Si tip for STM imaging. We integrate the on-chip STM into a commercial ultrahigh-vacuum STM system and perform imaging with atomic resolution on par with conventional STMs but at higher scan speeds due to the higher sensitivity of the MEMS actuator relative to a piezotube. The results attest that it is possible to achieve a parallel and high-throughput STM platform, which is a fully batch-fabricated MEMS STM nanopositioner capable of performing atomic-resolution STM imaging.

Instruments & Instrumentation↗
DOE OSTI2025

Productivity and cost of energy chipping with non-integrated harvesting systems in the Coastal Plain of the US south

Research from the 1980s–2010s suggested that integrated harvesting systems that harvest conventional products (e.g., sawtimber, pulpwood) and energy chips simultaneously were the most effective solution to produce energy chips in the US South. Alternatives, such as biomass-only systems, have important advantages in forest stands with low volumes of merchantable timber. The goal of this study was to estimate the productivity and cost of producing energy chips using non-integrated systems. Innovative chipping contractors using non-integrated systems were identified through contacts with procurement foresters responsible for purchasing energy chips. Elemental time-and-motion studies were conducted to estimate harvesting productivity on five operations, including one clearcut harvest and four first thinnings in overstocked stands. The hourly cost of equipment was estimated using the machine rate method. Cost per tonne was estimated by combining hourly productivity and hourly costs in a modified version of the Auburn Harvesting Analyzer. System productivity averaged 37 tonnes per scheduled machine hour (smh) and cut-and-haul costs averaged $33.86 t −1 (USD), which was comparable to previous estimates from integrated systems. In conclusion, this study suggests there are viable alternatives to integrated harvesting systems to produce energy chips, especially in stands with low volumes of merchantable timber.

09 BIOMASS FUELS↗
NASA NTRS1991

Test chips and ASIC qualification

A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.

Buehler, M. G.↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗
NASA NTRS2010

Quad-Chip Double-Balanced Frequency Tripler

Solid-state frequency multipliers are used to produce tunable broadband sources at millimeter and submillimeter wavelengths. The maximum power produced by a single chip is limited by the electrical breakdown of the semiconductor and by the thermal management properties of the chip. The solution is to split the drive power to a frequency tripler using waveguides to divide the power among four chips, then recombine the output power from the four chips back into a single waveguide. To achieve this, a waveguide branchline quadrature hybrid coupler splits a 100-GHz input signal into two paths with a 90 relative phase shift. These two paths are split again by a pair of waveguide Y-junctions. The signals from the four outputs of the Y-junctions are tripled in frequency using balanced Schottky diode frequency triplers before being recombined with another pair of Y-junctions. A final waveguide branchline quadrature hybrid coupler completes the combination. Using four chips instead of one enables using four-times higher power input, and produces a nearly four-fold power output as compared to using a single chip. The phase shifts introduced by the quadrature hybrid couplers provide isolation for the input and output waveguides, effectively eliminating standing waves between it and surrounding components. This is accomplished without introducing the high losses and expense of ferrite isolators. A practical use of this technology is to drive local oscillators as was demonstrated around 300 GHz for a heterodyne spectrometer operating in the 2-3-THz band. Heterodyne spectroscopy in this frequency band is especially valuable for astrophysics due to the presence of a very large number of molecular spectral lines. Besides high-resolution radar and spectrographic screening applications, this technology could also be useful for laboratory spectroscopy.

Lin, Robert H.↗
NASA NTRS2013

Automated, Ultra-Sterile Solid Sample Handling and Analysis on a Chip

There are no existing ultra-sterile lab-on-a-chip systems that can accept solid samples and perform complete chemical analyses without human intervention. The proposed solution is to demonstrate completely automated lab-on-a-chip manipulation of powdered solid samples, followed by on-chip liquid extraction and chemical analysis. This technology utilizes a newly invented glass micro-device for solid manipulation, which mates with existing lab-on-a-chip instrumentation. Devices are fabricated in a Class 10 cleanroom at the JPL MicroDevices Lab, and are plasma-cleaned before and after assembly. Solid samples enter the device through a drilled hole in the top. Existing micro-pumping technology is used to transfer milligrams of powdered sample into an extraction chamber where it is mixed with liquids to extract organic material. Subsequent chemical analysis is performed using portable microchip capillary electrophoresis systems (CE). These instruments have been used for ultra-highly sensitive (parts-per-trillion, pptr) analysis of organic compounds including amines, amino acids, aldehydes, ketones, carboxylic acids, and thiols. Fully autonomous amino acid analyses in liquids were demonstrated; however, to date there have been no reports of completely automated analysis of solid samples on chip. This approach utilizes an existing portable instrument that houses optics, high-voltage power supplies, and solenoids for fully autonomous microfluidic sample processing and CE analysis with laser-induced fluorescence (LIF) detection. Furthermore, the entire system can be sterilized and placed in a cleanroom environment for analyzing samples returned from extraterrestrial targets, if desired. This is an entirely new capability never demonstrated before. The ability to manipulate solid samples, coupled with lab-on-a-chip analysis technology, will enable ultraclean and ultrasensitive end-to-end analysis of samples that is orders of magnitude more sensitive than the ppb goal given in the Science Instruments.

Mora, Maria F.↗
NASA NTRS2015

Ion Chromatography-on-a-chip for Water Quality Analysis

We report progress towards developing a Micro-Electro-Mechanical Systems (MEMS)- based ion chromatograph (IC) for crewed spacecraft water analysis. This IC-chip is an offshoot of a NASA-funded effort to produce a high performance liquid chromatograph (HPLC)-chip. This HPLC-chip system would require a desalting (i.e. ion chromatography) step. The complete HPLC instrument consists of the Jet Propulsion Labortory's (JPL's) quadrupole ion trap mass spectrometer integrated with a state-of-the-art MEMS liquid chromatograph (LC) system developed by the California Institute of Technology's (Caltech's) Micromachining Laboratory. The IC version of the chip consist of an electrolysis-based injector, a separation column, two electrolysis pumps for gradient generation, mixer, and a built-in conductivity detector. The HPLC version of the chip also includes a nanospray tip. The low instrument mass, coupled with its high analytical capabilities, makes the LC chip ideally suitable for wide range of applications such as trace contaminant, inorganic analytical science and, when coupled to a mass spectrometer, a macromolecular detection system for either crewed space exploration vehicles or robotic planetary missions.

Kidd, R. D.↗
DOE OSTI2021

Convolutional Neural Networks for the CHIPS Neutrino Detector R&D Project.

The CHerenkov detectors In mine PitS (Chips) neutrino detector R&D project aims to develop novel strategies and technologies for very large yet ‘cheap as chips’ water Cherenkov neutrino detectors. Via deployment in a body of water, use of commercially available components, and instrumentation coverage optimisation for the study of exclusively accelerator beam neutrinos, Chips will enable megaton scale detectors to become a reality at the cost of $200k-$300k per kt of sensitive mass. During the summer of 2019 a prototype Chips detector, Chips-5, was deployed into the Wentworth 2W disused mine pit in northern Minnesota, 7 mrad off the NuMI beam axis. A novel data acquisition system was introduced using cheap single-board computers and open-source software. This work presents a novel approach to water Cherenkov neutrino detector event reconstruction and classification. Three forms of a Convolutional Neural Network, a type of deep learning algorithm, have been trained to reject cosmic muon events, classify beam events, and estimate neutrino energies, all using only the raw detector event as input. When evaluated on the expected distribution of Chips-5 events, this new approach is shown to be robust and explainable as well as providing a significant performance increase over the standard likelihood-based reconstruction and simple neural network classification. Promisingly, the performance presented here is comparable to the more complex (and expensive) neutrino oscillation experiments within the field.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Multi-chip photonics transceiver

A photonics transceiver is described herein, wherein the photonics transceiver exhibits improved areal bandwidth density and improved energy per bit consumption relative to conventional photonics transceivers. The photonics transceiver achieves an areal bandwidth density of at least 5 Tbps/mm2 with an energy consumption of less than 500 fJ/bit (sum of energy consumed for both a transmitted bit and a received bit). The photonics transceiver is a multi-chip module, where chips in the multi-chip module are tightly integrated with one another. The multi-chip module includes light source, photodetector, photonics, and control/logic chips. The photonics chip includes transparent conducting oxide integrated optical modulators and multiplexers and demultiplexers based on MEMS-tunable optical ring resonators.

Wood, Michael↗
DOE OSTI2014

Shielding design for a chip irradiation test facility at SNS - Paper 119

As digital and analog circuits are more and more sophisticatedly integrated, they become increasingly susceptible to single event upsets (SEU), a cause of electronic equipment malfunction induced by cosmic rays with particular hazard potential for aviation equipment. Electronic chips sensitive to SEU have to be tested in a simulated comic ray environment to ensure their reliability. It is found that the spallation induced fast neutron spectrum is very close to the neutron spectrum of the cosmic ray. Hence, a conceptual design study of a chip irradiation test facility is funded by FAA to be carried out at SNS, the world's most powerful accelerator driven facility for neutron scattering studies on materials. Compared to existing/being construct chip irradiation test facilities at LANL and ISIS, SNS can provide wider neutron energy range and much higher fluxes. This study focuses on the aspect of shielding design for such a chip irradiation facility. A number of medium-weighted and heavy materials were examined for efficiency in reducing radiation dose rate. In general, the smaller the target monolith is while satisfying the personnel-protection-driven radiation dose rate limit at its outside, the closer to the target chips could be placed and thus less beam power it demands to satisfy a given irradiation flux requirement. Before proceed to the shielding design, the neutron source coming off the target has to be determined for selecting a best spot for chip irradiation test, in which the incoming fast neutron spectrum approximate most to the atmospheric radiation condition. It also provides a source term for the following shielding design of the irradiation enclosure. (authors)

36 MATERIALS SCIENCE↗
DOE OSTI2022

An optimized ChIP-Seq framework for profiling histone modifications in Chromochloris zofingiensis

The eukaryotic green alga Chromochloris zofingiensis is a reference organism for studying carbon partitioning and a promising candidate for the production of biofuel precursors. Recent transcriptome profiling transformed our understanding of its biology and generally algal biology, but epigenetic regulation remains understudied and represents a fundamental gap in our understanding of algal gene expression. Chromatin immunoprecipitation followed by deep sequencing (ChIP-Seq) is a powerful tool for the discovery of such mechanisms, by identifying genome-wide histone modification patterns and transcription factor-binding sites alike. Here, we established a ChIP-Seq framework for Chr. zofingiensis yielding over 20 million high-quality reads per sample. The most critical steps in a ChIP experiment were optimized, including DNA shearing to obtain an average DNA fragment size of 250 bp and assessment of the recommended formaldehyde concentration for optimal DNA-protein cross-linking. We used this ChIP-Seq framework to generate a genome-wide map of the H3K4me3 distribution pattern and to integrate these data with matching RNA-Seq data. In line with observations from other organisms, H3K4me3 marks predominantly transcription start sites of genes. Our H3K4me3 ChIP-Seq data will pave the way for improved genome structural annotation in the emerging reference alga Chr. zofingiensis.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2018

Test results and prospects for RD53A, a large scale 65 nm CMOS chip for pixel readout at the HL-LHC

The CERN RD53 collaboration was founded to tackle the extraordinary challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments. Around 20 institutions are involved in the collaboration, which has the support of both ATLAS and CMS experiments. The goals of the collaboration include the comprehensive understanding of radiation effects in the 65 nm technology, the development of tools and methodology to efficiently design large complex mixed signal chips and, ultimately, the development of a full size readout chip featuring a 400 × 400 pixel array with 50μm pitch. In August 2017, the collaboration submitted the large scale chip RD53A, integrating a matrix of 400 × 192 pixels and embodying three different analog front-end designs. Here, this work discusses the characteristic of the RD53A chip, with some emphasis on the analog processors, and presents the first test results on the pixel array.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

System-on-Chip approach microwave diagnostics development for burning plasma

System-on-chip (SoC) millimeter wave integrated circuit technology has been developed and employed in chip heterodyne radiometers in Electron Cyclotron Emission Imaging (ECEI) and Microwave Imaging Reflectometer (MIR) on the DIII-D tokamak for 2D electron temperature and density fluctuation diagnostics. The W-band (75-110 GHz) ECEI system has been employed with 20 poloidal horn receiver modules with customized monolithic integrated circuit chips and internal local oscillator coupling path. The new SoC approach demonstrates > 30 dB additional gain on the receiver and 95% electronics noise suppression compared to the previous Schottky diode mixer array . An F-band (110-140 GHz) receiver chip has been developed to measure MHD and turbulence behavior on the DIII-D high-field side, such as Alfven eigenmodes. Furthermore, it can image pedestal structure evolution on fusion facilities with stronger magnetic fields, such as ASDEX-U, EAST, HL-2M, and LHD. The F-band chip performance has been tested in the laboratory. Also, V-band (55-75 GHz) transmitter and receiver modules (55-75 GHz) have been developed for DIII-D and NSTX-U Furthermore, microwave Imaging Reflectometer (MIR) application suitability for 2D density fluctuation imaging on the pedestal region.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2013

Integrated Power Chip Converter for Solid State Lighting (Final Report)

The overall goal of the project was to develop an integrated power converter chip for solid-state lighting. We developed a low component count circuit topology, fast and low loss switching devices, compact and low loss passive components, and integration methodology to enable an integrated LED driver, where cost, size and efficiency are paramount. The converter was designed to operate directly from ac line voltage, nominally providing 24 V output at 25 W with features of dimming and control for light uniformity. We developed a power circuit and control suitable for chip-scale integration, low loss and high frequency GaN power devices with a new vertical architecture that reduces parasitics and lowers cost by decreasing the chip real estate, and high-density passives, including a chip-scale flyback transformer that integrates inductor and transformer action into a single component.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2012

Control of a Bose-Einstein condensate on a chip by external optical and magnetic potentials

In this paper we explore the possibilities of control of a Bose-Einstein condensate on an atom chip by the use of potentials generated by photonic and magnetic components. We show that the fields produced by both types of components can be modelled by a generic exponential potential and derive analytic expressions that allow for an easy assessment of their impact on a trapped condensate. Using dynamical numerical simulations we study the transport of the condensate between the control structures on a chip. We study in detail different regimes of the condensate behaviour in an evanescent light potential generated by a photonic structure in the vicinity of the condensate and in magnetic potentials generated by a wire or a coil. The calculations are based on the reported parameters of atom chip setups and available photonic and magnetic components. Finally, the model is verified by an experiment with a condensate on an atom chip and a coil. - Highlights: Black-Right-Pointing-Pointer Generic potential used to describe both the optical evanescent and magnetic fields. Black-Right-Pointing-Pointer An analytic closed form solution found for the impact of a generic potential on a BEC. Black-Right-Pointing-Pointer BEC dynamics calculated for potential time sequences attainable in experiments. Black-Right-Pointing-Pointer Conditions for BEC transfer by an external field identified. Black-Right-Pointing-Pointer Exponential-potential model validated by a BEC-on-chip experiment.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗