SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
We have described a challenging neural-network hardware implementation that would mate a 64x64-pixel infrared sensor directly on to a 3-dimensionally packaged set of neural processing chips with parallel input for high speed image processing. Non linearity effects and range compression are also discussed.
The utility of a high-density oligonucleotide microarray (microchip) for identifying strains of five closely related bacilli (Bacillus anthracis, Bacillus cereus, Bacillus mycoides, Bacillus medusa and Bacillus subtilis) was demonstrated using an approach that compares the non-equilibrium dissociation rates ('melting curves') of all probe-target duplexes simultaneously. For this study, a hierarchical set of 30 oligonucleotide probes targeting the 16S ribosomal RNA of these bacilli at multiple levels of specificity (approximate taxonomic ranks of domain, kingdom, order, genus and species) was designed and immobilized in a high-density matrix of gel pads on a glass slide. Reproducible melting curves for probes with different levels of specificity were obtained using an optimized salt concentration. Clear discrimination between perfect match (PM) and mismatch (MM) duplexes was achieved. By normalizing the signals to an internal standard (a universal probe), a more than twofold discrimination (> 2.4x) was achieved between PM and 1-MM duplexes at the dissociation temperature at which 50% of the probe-target duplexes remained intact. This provided excellent differentiation among representatives of different Bacillus species, both individually and in mixtures of two or three. The overall pattern of hybridization derived from this hierarchical probe set also provided a clear 'chip fingerprint' for each of these closely related Bacillus species.
A neural network experiment conducted for the Space Technology Research Vehicle (STRV-1) 1-b launched in June 1994. Identical sets of analog feed-forward neural network chips was used to study and compare the effects of space and ground radiation on the chips. Three failure mechanisms are noted.
The increased use of on-chip cache memories has led researchers to investigate their performance in the presence of manufacturing defects. Several techniques for yield improvement are discussed and results are presented which indicate that set-associativity may be used to provide defect tolerance as well as improve the cache performance. Tradeoffs between several cache organizations and replacement strategies are investigated and it is shown that token-based replacement may be a suitable alternative to the widely-used LRU strategy.
The primary goal of the Adaptive Vision Laboratory Research project was to develop advanced computer vision systems for automatic target recognition. The approach used in this effort combined several machine learning paradigms including evolutionary learning algorithms, neural networks, and adaptive clustering techniques to develop the E-MOR.PH system. This system is capable of generating pattern recognition systems to solve a wide variety of complex recognition tasks. A series of simulation experiments were conducted using E-MORPH to solve problems in OCR, military target recognition, industrial inspection, and medical image analysis. The bulk of the funds provided through this grant were used to purchase computer hardware and software to support these computationally intensive simulations. The payoff from this effort is the reduced need for human involvement in the design and implementation of recognition systems. We have shown that the techniques used in E-MORPH are generic and readily transition to other problem domains. Specifically, E-MORPH is multi-phase evolutionary leaming system that evolves cooperative sets of features detectors and combines their response using an adaptive classifier to form a complete pattern recognition system. The system can operate on binary or grayscale images. In our most recent experiments, we used multi-resolution images that are formed by applying a Gabor wavelet transform to a set of grayscale input images. To begin the leaming process, candidate chips are extracted from the multi-resolution images to form a training set and a test set. A population of detector sets is randomly initialized to start the evolutionary process. Using a combination of evolutionary programming and genetic algorithms, the feature detectors are enhanced to solve a recognition problem. The design of E-MORPH and recognition results for a complex problem in medical image analysis are described at the end of this report. The specific task involves the identification of vertebrae in x-ray images of human spinal columns. This problem is extremely challenging because the individual vertebra exhibit variation in shape, scale, orientation, and contrast. E-MORPH generated several accurate recognition systems to solve this task. This dual use of this ATR technology clearly demonstrates the flexibility and power of our approach.
A quick and preliminary comparison is made between the Intel 386 and i486 microprocessors. The following topics are discussed: the i486 key elements, comparison of instruction set architecture, the i486 on-chip cache characteristics, the i486 multiprocessor support, comparison of performance, comparison of power consumption, comparison of radiation hardening potential, and recommendations for the Space Station Freedom (SSF) Data Management System (DMS).
Over the past decade, electronic, electrical, and electromechanical (EEE) parts for space applications have undergone significant changes, largely driven by CubeSat and commercial space developers pushing the boundaries on the utilization of commercial parts in space. Global product shortages and shipping delays are still impacting space flight project deadlines. Many projects have turned to automotive grade resistors as an alternate to their MIL-SPEC counterparts to fulfill requirements. In addition, automotive grade resistors may offer designers a wider range of parts to consider. A recent NASA study recommended the use of high-volume manufactured commercial components for space applications provided these components show evidence of stringent fabrication controls and thorough reliability monitoring practices [1]. Automotive grade components have stringent qualification requirements per the Automotive Electronic Council (AEC). However, the end user usually does not have insight into the practices the manufacturer may use to reduce/eliminate infant mortality nor for compliance to all datasheet specifications. Screening, Life and Accelerated Life testing on a set of standard automotive-grade chip resistors is proposed to evaluate the reliability of these components. Requirements from both the AEC-Q (Automotive Electronic Council Qualification) and EEE-INST-002 (Instructions for EEE Parts Selection, Screening, Qualification, and Derating) for resistors is compared and discussed. The resistors have been tested by using a modified methodology from EEE-INST-002 to evaluate their reliability for space flight projects. The findings of this study indicate that the underlying degradation mechanisms at rated temperature and power are best represented by power law models with a fitted exponent between 0 and 1. A linear model is more conservative which compensates for potential model uncertainty given the wide range of design and materials used in automotive resistors, while still providing useful long-term resistance drift estimates. No electrical anomalies or failures were observed throughout the 1,000-hour Life Tests other than small in tolerance resistance drift aging. Degradation models were utilized to quantify and extrapolate the long-term resistance drift under operating conditions for the components. The models demonstrated that some automotive-grade resistors are likely to operate 10 years at nominal usage conditions while others might fail earlier.
Over the past decade, electronic, electrical, and electromechanical (EEE) parts for space applications have undergone significant changes, largely driven by CubeSat and commercial space developers pushing the boundaries on the utilization of commercial parts in space. Global product shortages and shipping delays are still impacting space flight project deadlines. Many projects have turned to automotive grade resistors as an alternate to their MILSPEC counterparts to fulfill requirements. In addition, automotive grade resistors may offer designers a wider range of parts to consider. A recent NASA study recommended the use of high-volume manufactured commercial components for space applications provided these components show evidence of stringent fabrication controls and thorough reliability monitoring practices. Automotive grade components have stringent qualification requirements per the Automotive Electronic Council (AEC). However, the end user usually does not have insight into the practices the manufacturer may use to reduce/eliminate infant mortality nor for compliance to all datasheet specifications. Screening, Life and Accelerated Life testing on a set of standard automotive-grade chip resistors is proposed to evaluate the reliability of these components. Requirements from both the AEC-Q (Automotive Electronic Council Qualification) and EEE-INST-002 (Instructions for EEE Parts Selection, Screening, Qualification, and Derating) for resistors is compared and discussed. The resistors have been tested by using a modified methodology from EEEINST-002 to evaluate their reliability for space flight projects. The findings of this study indicate that the underlying degradation mechanisms at rated temperature and power are best represented by power law models with a fitted exponent between 0 and 1. A linear model is more conservative which compensates for potential model uncertainty given the wide range of design and materials used in automotive resistors, while still providing useful long-term resistance drift estimates. No electrical anomalies or failures were observed throughout the 1000-hour Life Tests other than small in tolerance resistance drift aging. Degradation models were utilized to quantify and extrapolate the long-term resistance drift under operating conditions for the components. The models demonstrated that some automotive-grade resistors are likely to operate 10 years at nominal usage conditions while others might fail earlier.
A CCD technique is described which allows long integration periods between readouts together with moderate chopping rates. During each phase of a differential chopping cycle, one set of charge images is shifted to the center of the chip, which is light sensitive. At the same time, the other set of charge images is shifted under one of two masked areas which serve as charge-storage sites. Since the vertical shifting between phases can be accomplished in much less time than the typical exposure per phase, there is negligible image smearing. For a given light level and chopping rate the performance of this technique is limited primarily by the readout noise and the vertical charge transfer inefficiency. If many transfer cycles are required between readouts, the charge transfer inefficiency will diffuse the accumulated charge images along the vertical columns. Laboratory and astronomical data obtained with this technique using a CCD camera and the 2.3 m telescope on Kitt Peak are presented.
A series of bench top experiments was conducted to determine the effects of metallic debris being dragged through meshing gear teeth. A test rig that is typically used to conduct contact fatigue experiments was used for these tests. Several sizes of drill material, shim stock, and pieces of gear teeth were introduced and then driven through the meshing region. The level of torque required to drive the "chip" through the gear mesh was measured. From the data gathered, chip size sufficient to jam the mechanism can be determined. INTRODUCTION In some space mechanisms the loading can be so high that there is some possibility that a gear chip might be liberated while in operation of the mechanism [1-5]. Also, due to the closely packed nature of some space mechanisms and the fact that a space grease is used for lubrication, chips that are released can then be introduced to other gear meshes within this mechanism. In this instance, it is desirable to know the consequences of a gear chip entering in between meshing gear teeth. To help provide some understanding, a series of bench-top experiments was conducted to engage chips of simulated and gear material fragments into a meshing gear pair. One purpose of the experiments was to determine the relationship of chip size to the torque required to rotate the gear set through the mesh cycle. The second purpose was to determine the condition of the gear chip material after engagement by the meshing gears, primarily to determine if the chip would break into pieces and to observe the motion of the chip as the engagement was completed. This document also presents preliminary testing done with metal debris other than chips from gears, namely steel shim stock and drill bits of various sizes and diameters.
The design and evaluation of a novel fixturing technique for characterizing millimeter wave solid state devices is presented. The technique utilizes a cosine-tapered ridge guide fixture and a one-tier de-embedding procedure to produce accurate and repeatable device level data. Advanced features of this technique include nondestructive testing, full waveguide bandwidth operation, universality of application, and rapid, yet repeatable, chip-level characterization. In addition, only one set of calibration standards is required regardless of the device geometry.
Data-processing system exploits high speeds inherent in optical elements. Instruction sets for different computer operations reside on different external memory chips. Laser diodes activated for each operation generate light, reflected by holographic optical element to designated receptors in arithmetic and logic unit. Pattern of light beams embodies instruction set at given instant. With potential ability to reprogram in real time, conceptual system applicable to task-driven programming or artificial intelligence.
The Multi-Anode Microchannel Array (MAMA) is a photon counting detector which utilizes a photocathode for photon to electron conversion, a microchannel plate (MCP) for signal amplification and a proximity focused anode array for position sensitivity. The detector electronics decode the position of an event through coincidence discrimination. The decoding algorithm which associates a given event with the appropriate pixel is determined by the geometry of the array. A new algorithm incorporated into a CMOS Application Specific Integrated Circuit (ASIC) decoder which improves the pixel spatial resolution is described. The new algorithm does not degrade the detector throughput and does not require any modifications to the detector tube. The standard MAMA detector has a pixel size of 25 x 25 square microns, but with the new decoder circuit the pixel size is reduced to 12.5 x 12.5 square microns. We have built the first set of decode electronics utilizing the new ASIC chips and report here on the first imaging tests of this system.
The Wide-field Imaging Interferometry Testbed (WIIT) is a double Fourier (DF) interferometer operating at optical wavelengths, and provides data that are highly representative of those from a space-based far-infrared interferometer like SPIRIT. We have used the testbed to observe both geometrically simple and astronomically representative test scenes. Here we present an overview of the astronomical importance of high angular resolution at the far infrared, followed by the description of the optical set-up of WIIT, including the source simulator CHIP (Calibrated Hyperspectral Image Projector). We describe our synthesis algorithms used in the reconstruction of the input test scenes via a simulation of the most recent measurements. The updated algorithms, which include instruments artifacts that allow the synthesis of DF experimental data, are presented and the most recent results analyzed.
The cascade back-propagation (CBP) algorithm is the basis of a conceptual design for accelerating learning in artificial neural networks. The neural networks would be implemented as analog very-large-scale integrated (VLSI) circuits, and circuits to implement the CBP algorithm would be fabricated on the same VLSI circuit chips with the neural networks. Heretofore, artificial neural networks have learned slowly because it has been necessary to train them via software, for lack of a good on-chip learning technique. The CBP algorithm is an on-chip technique that provides for continuous learning in real time. Artificial neural networks are trained by example: A network is presented with training inputs for which the correct outputs are known, and the algorithm strives to adjust the weights of synaptic connections in the network to make the actual outputs approach the correct outputs. The input data are generally divided into three parts. Two of the parts, called the "training" and "cross-validation" sets, respectively, must be such that the corresponding input/output pairs are known. During training, the cross-validation set enables verification of the status of the input-to-output transformation learned by the network to avoid over-learning. The third part of the data, termed the "test" set, consists of the inputs that are required to be transformed into outputs; this set may or may not include the training set and/or the cross-validation set. Proposed neural-network circuitry for on-chip learning would be divided into two distinct networks; one for training and one for validation. Both networks would share the same synaptic weights.
A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.
We report progress on using a new type of amplifier, the Radio-Frequency Single-Electron Transistor (RF-SET), to develop multi-channel sensor readout systems for fast and sensitive readout of high impedance cryogenic photodetectors such as Superconducting Tunnel Junctions and Single Quasiparticle Photon Counters. Although cryogenic, these detectors are desirable because of capabilities not other-wise attainable. However, high impedances and low output levels make low-noise, high-speed readouts challenging, and large format arrays would be facilitated by compact, low-power, on-chip integrated amplifiers. Well-suited for this application are RF-SETs, very high performance electrometers which use an rf readout technique to provide 100 MHz bandwidth. Small size, low power, and cryogenic operation allow direct integration with detectors, and using multiple rf carrier frequencies permits simultaneous readout of 20-50 amplifiers with a common electrical connection. We describe both the first 2-channel demonstration of this wavelength division multiplexing technique for RF-SETs, and Charge-Locked-Loop operation with 100 kHz of closed-loop bandwidth.
The NASA-Cornell Univ.-Worcester Polytechnic Institute Fast Fourier Transform (FFT) chip based on the architecture of the systolic FFT computation as presented by Boriakoff is implemented into an operating device design. The kernel of the system, a systolic inner product floating point processor, was designed to be assembled into a systolic network that would take incoming data streams in pipeline fashion and provide an FFT output at the same rate, word by word. It was thoroughly simulated for proper operation, and it has passed a comprehensive set of tests showing no operational errors. The black box specifications of the chip, which conform to the initial requirements of the design as specified by NASA, are given. The five subcells are described and their high level function description, logic diagrams, and simulation results are presented. Some modification of the Read Only Memory (ROM) design were made, since some errors were found in it. Because a four stage pipeline structure was used, simulating such a structure is more difficult than an ordinary structure. Simulation methods are discussed. Chip signal protocols and chip pinout are explained.