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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Study presents methods and initial procedures which may be obtained for development of more efficient uniform network analysis input language and theoretical tools to prove equivalence of data representations.
A methodology for optimizing power-processor designs is described which achieves optimization with respect to some power-processor characteristic deemed particularly desirable by the designer, such as weight or efficiency. Optimization theory based on Lagrange multipliers is reviewed together with nonlinear programming techniques employing penalty functions. The methodology, the task of which is to minimize an objective function subject to design constraints, is demonstrated with the aid of four examples: optimum-weight core selection for an inductor with a predetermined winding size, optimum-weight inductor design with a given loss constraint, optimum-loss inductor design with a given weight constraint, and a comparison of optimum-weight single- and two-stage input-filter designs with identical loss and other requirement constraints. Closed-form solutions for the first three examples are obtained by applying the Lagrange-multiplier method, but solutions for the last example are found numerically through the use of the sequential unconstrained minimization technique.
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This paper will address several aspects of the design and construction of submodules based on thin film amorphous silicon (a-Si) p i n solar cells. Starting from presently attainable single cell characteristics, and a realistic set of specifications, practical module designs are discussed from the viewpoints of efficient designs, the fabrication requirements, and reliability concerns. The examples center mostly on series interconnected modules of the superstrate type with detailed discussions of each portion of the structure in relation to its influence on module efficiency. Emphasis is placed on engineering topics such as: area coverage, optimal geometries, and cost and reliability. Practical constraints on achieving optimal designs, along with some examples of potential pitfalls in the manufacture and subsequent performance of a-Si modules are discussed.
Progress in the development of solar heating modular control subsystems is reported. Circuit design, circuit drawings, and printed circuit board layout are discussed along with maintenance manuals, installation instructions, and verification and acceptance tests. Calculations made to determine the predicted performance of the differential thermostat are given including details and results of tests for the offset temperature, and boil and freeze protect points.
Design procedure for production of radiation resistant NOR gate logic circuit
Design rules for Layered Ridge Dielectric Waveguide (LRDW) are presented for the first time through simple figures and closed form equations. The Effective Dielectric Constant (EDC) method is used to develop the design rules that account for typical circuit specifications such as higher order mode suppression, dispersion, attenuation, and coupling between adjacent transmission lines. Comparisons between the design of LRDW, image guide, and millimeter-wave dielectric ridge guide are made.
Guide for designing printed circuits and circuit boards
Single-mesh circuits design for driving xenon flashlamps, solving normalized nonlinear differential equation
The goal of this research is to investigate the application of evolutionary search to the process of automated engineering design. Evolutionary search techniques involve the simulation of Darwinian mechanisms by computer algorithms. In recent years, such techniques have attracted much attention because they are able to tackle a wide variety of difficult problems and frequently produce acceptable solutions. The results obtained are usually functional, often surprising, and typically "messy" because the algorithms are told to concentrate on the overriding objective and not elegance or simplicity. advantages. First, faster design cycles translate into time and, hence, cost savings. Second, automated design techniques can be made to scale well and hence better deal with increasing amounts of design complexity. Third, design quality can increase because design properties can be specified a priori. For example, size and weight specifications of a device, smaller and lighter than the best known design, might be optimized by the automated design technique. The domain of electronic circuit design is an advantageous platform in which to study automated design techniques because it is a rich design space that is well understood, permitting human-created designs to be compared to machine- generated designs. developed for circuit design was to automatically produce high-level integrated electronic circuit designs whose properties permit physical implementation in silicon. This process entailed designing an effective evolutionary algorithm and solving a difficult multiobjective optimization problem. FY 99 saw many accomplishments in this effort.
Design criteria for solid state electronic, high speed iterative differential analyzer using integrated circuits
Electronic circuits and systems designed for deep space missions need to operate reliably and efficiently in harsh environments that include very low temperatures. Spacecraft that operate in such cold environments carry a large number of heaters so that the ambient temperature for the onboard electronics remains near 20 C. Electronics that can operate at cryogenic temperatures will simplify system design and reduce system size and weight by eliminating the heaters and their associated structures. As a result, system development and launch cost will be reduced. At the NASA Glenn Research Center, an ongoing program is focusing on the development of power electronics geared for deep space low-temperature environments. The research and development efforts include electrical components design, circuit design and construction, and system integration and demonstration at cryogenic temperatures. Investigations are being carried out on circuits and systems that are targeted for use in NASA missions where low temperatures will be encountered: devices such as ceramic and tantalum capacitors, metal film resistors, semiconductor switches, magnetics, and integrated circuits including dc/dc converters, operational amplifiers, voltage references, and motor controllers. Test activities cover a wide range of device and circuit performance under simple as well as complex test conditions, such as multistress and thermal cycling. The effect of low-temperature conditions on the switching characteristics of an advanced silicon-on-insulator field effect transistor is shown. For gate voltages (VGS) below 2.6 V, drain currents at -190 C are lower than drain currents at room temperature (20 C).
Pyrotechnic systems often fall into a unique category in that inadvertent activation of these systems resulting from a fault and/or lack of safe margins can lead directly to loss of crew. For example, untimely activation of pyrotechnics used for a flight termination system could override an abort capability. Over the years, NASA and the military have learned lessons about safe pyrotechnic circuit design and test, many of which are codified. However, with NASA’s recent efforts to move toward a development model than leans more heavily on Commercial Partners these requirements have not always been directly levied on projects and in some cases been misinterpreted. This bulletin describes key safety features of pyrotechnic firing circuit design and provides rationale for inclusion of each feature.
Design methods for asynchronous sequential pass-transistor circuits, which result in circuits that are hazard- and critical-race-free and which have added degrees of freedom for the input signals, are discussed. The design procedures are straightforward and easy to implement. Two single-transition-time state assignment methods are presented, and hardware bounds for each are established. A surprising result is that the hardware realizations for each next state variable and output variable is identical for a given flow table. Thus, a state machine with N states and M outputs can be constructed using a single layout replicated N + M times.
In order to design a quantum circuit that performs a desired quantum computation, it is necessary to find a decomposition of the unitary matrix that represents that computation in terms of a sequence of quantum gate operations. To date, such designs have either been found by hand or by exhaustive enumeration of all possible circuit topologies. In this paper we propose an automated approach to quantum circuit design using search heuristics based on principles abstracted from evolutionary genetics, i.e. using a genetic programming algorithm adapted specially for this problem. We demonstrate the method on the task of discovering quantum circuit designs for quantum teleportation. We show that to find a given known circuit design (one which was hand-crafted by a human), the method considers roughly an order of magnitude fewer designs than naive enumeration. In addition, the method finds novel circuit designs superior to those previously known.
According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.
Topographic simulation scheme used to program path layout of conductors in printed circuit board design