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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1989

Advanced technology satellite demodulator development

Ford Aerospace has developed a proof-of-concept satellite 8 phase shift keying (PSK) modulation and coding system operating in the Time Division Multiple Access (TDMA) mode at a data range of 200 Mbps using rate 5/6 forward error correction coding. The 80 Msps 8 PSK modem was developed in a mostly digital form and is amenable to an ASIC realization in the next phase of development. The codec was developed as a paper design only. The power efficiency goal was to be within 2 dB of theoretical at a bit error rate (BER) of 5x10(exp 7) while the measured implementation loss was 4.5 dB. The bandwidth efficiency goal was 2 bits/sec/Hz while the realized bandwidth efficiency was 1.8 bits/sec/Hz. The burst format used a preamble of only 40 8 PSK symbol times including 32 symbols of all zeros and an eight symbol unique word. The modem and associated special test equipment (STE) were fabricated mostly on a specially designed stitch-weld board although a few of the highest rate circuits were built on printed circuit cards. All the digital circuits were ECL to support the clock rates of from 80 MHz to 360 MHz. The transmitter and receiver matched filters were square-root Nyquist bandpass filters realized at the 3.37 GHz i.f. The modem operated as a coherent system although no analog phase locked (PLL) loop was employed. Within the budgetary constraints of the program, the approach to the demodulator has been proven and is eligible to proceed to the next phase of development of a satellite demodulator engineering model. This would entail the development of an ASIC version of the digital portion of the demodulator, and MMIC version of the quadrature detector, and SAW Nyquist filters to realize the bandwidth efficiency.

Ames, Stephen A.↗
NASA NTRS1979

Flight test evaluation of a digital controller used in a VTOL automatic approach and landing system

As part of the NASA Langley Research Center's effort to develop technology for VTOL operation in the air transportation system in the late 1980's and beyond, research has been conducted aimed at developing digital controller design procedures. This paper describes the verification of one design procedure by the flight evaluation of an advanced digital control algorithm. The control algorithm, operating at 10 iterations per second, follows step guidance commands with zero steady state error and thus provides an autotrim capability for the nonlinear vehicle. Changes in vehicle dynamics are accounted for using a gain scheduling technique. This control algorithm is combined with sensor filters, a trajectory generator, and a closed loop guidance algorithm to form a VTOL autoland system. A CH-47 tandem rotor helicopter which contains a set of sensors, onboard digital flight computers and electro-hydraulic actuators is used in the evaluation. All software, except input-output routines, is coded in FORTRAN using floating point arithmetic and executed in the flight computer. This autoland system is exercised by automatically flying straight-in descending decelerating trajectories typical of VFR manual approaches to a predetermined landing pad.

Downing, D. R.↗
NASA NTRS1985

Signal Processor for Multirate PSK Signals

Any of six different data formats at any of five different data rates from phase-shift-key (PSK) modulated input signal extracted by digital radio receiver. Subcarrier Demodulator is Costas loop with hard limiter in inphase arm. There are six low-pass filters, each selectable for rate and format of data to be processed.

Helgesen, R. J.↗
NASA NTRS2005

Coupled Receiver/Decoders for Low-Rate Turbo Codes

been proposed for receiving weak single- channel phase-modulated radio signals bearing low-rate-turbo-coded binary data. Originally intended for use in receiving telemetry signals from distant spacecraft, the proposed receiver/ decoders may also provide enhanced reception in mobile radiotelephone systems. A radio signal of the type to which the proposal applies comprises a residual carrier signal and a phase-modulated data signal. The residual carrier signal is needed as a phase reference for demodulation as a prerequisite to decoding. Low-rate turbo codes afford high coding gains and thereby enable the extraction of data from arriving radio signals that might otherwise be too weak. In the case of a conventional receiver, if the signal-to-noise ratio (specifically, the symbol energy to one-sided noise power spectral density) of the arriving signal is below approximately 0 dB, then there may not be enough energy per symbol to enable the receiver to recover properly the carrier phase. One could solve the problem at the transmitter by diverting some power from the data signal to the residual carrier. A better solution . a coupled receiver/decoder according to the proposal . could reduce the needed amount of residual carrier power. In all that follows, it is to be understood that all processing would be digital and the incoming signals to be processed would be, more precisely, outputs of analog-to-digital converters that preprocess the residual carrier and data signals at a rate of multiple samples per symbol. The upper part of the figure depicts a conventional receiving system, in which the receiver and decoder are uncoupled, and which is also called a non-data-aided system because output data from the decoder are not used in the receiver to aid in recovering the carrier phase. The receiver tracks the carrier phase from the residual carrier signal and uses the carrier phase to wipe phase noise off the data signal. The receiver typically includes a phase-locked loop (PLL) or Costas loop that requires no delay or perhaps a single sample delay. The lower part of the figure depicts a basic coupled receiver/decoder . a data-aided system that would implement an iterative receiving/decoding process. The receiver would include a PLL or a Wiener filter that, to the extent possible, would track the residual carrier signal, wipe phase noise off the data signal, then send the result to the turbo decoder. Recovery of timing could be effected by, for example, a digital transition tracking loop (DTTL) or other, similar loop. The first iteration of turbo decoding would yield soft data symbols, which would be sent back to the receiver for use in softly wiping off the data signal in an effort to recover the residual carrier signal. The wiped signal would contain a relatively large carrier-phase component that could be tracked by use of a second Wiener filter.

Hamkins, Jon↗
NASA NTRS1975

Technical guidance and analytic services in support of SEASAT-A

The design of a high resolution radar for altimetry and ocean wave height estimation was studied. From basic principles, it is shown that a short pulse wide beam radar is the most appropriate and recommended technique for measuring both altitude and ocean wave height. To achieve a topographic resolution of + or - 10 cm RMS at 5.0 meter RMS wave heights, as required for SEASAT-A, it is recommended that the altimeter design include an onboard adaptive processor. The resulting design, which assumes a maximum likelihood estimation (MLE) processor, is shown to satisfy all performance requirements. A design summary is given for the recommended radar altimeter, which includes a full deramp STRETCH pulse compression technique followed by an analog filter bank to separate range returns as well as the assumed MLE processor. The feedback loop implementation of the MLE on a digital computer was examined in detail, and computer size, estimation accuracies, and bias due to range sidelobes are given for the MLE with typical SEASAT-A parameters. The standard deviation of the altitude estimate was developed and evaluated for several adaptive and nonadaptive split-gate trackers. Split-gate tracker biases due to range sidelobes and transmitter noise are examined. An approximate closed form solution for the altimeter power return is derived and evaluated. The feasibility of utilizing the basic radar altimeter design for the measurement of ocean wave spectra was examined.

Brooks, W. L.↗
NASA NTRS1977

A high-speed computer link for moderate distances and noisy environments

To satisfy the need for a fully duplex high-speed computer data link for the antenna automation project at DSS 13, a very simple and inexpensive scheme was employed. The link requires two coaxial cables over which is sent a unipolar digital frequency modulated signal in which a logical 1 has twice the frequency of a logical 0. Optical isolators and filters reduce ground loop effects and increase noise immunity. Tests conducted in various environments and over different cable lengths at JPL, DSS 14 and DSS 13 have indicated that the link is highly effective.

Sievers, M. W.↗
NASA NTRS2010

SEU/SET Tolerant Phase-Locked Loops

The phase-locked loop (PLL) is an old and widely used circuit for frequency and phase demodulation, carrier and clock recovery, and frequency synthesis [1]. Its implementations range from discrete components to fully integrated circuits and even to firmware or software. Often the PLL is a highly critical component of a system, as for example when it is used to derive the on-chip clock, but as of this writing no definitive single-event upset (SET)/single-event transient (SET) tolerant PLL circuit has been described. This chapter hopes to rectify that situation, at least in regard to PLLs that are used to generate clocks. Older literature on fault-tolerant PLLs deals with detection of a hard failure, which is recovered by replacement, repair, or manual restart of discrete component systems. Several patents exist along these lines (6349391, 6272647, and 7089442). A newer approach is to harden the parts of a PLL system, to one degree or another, such as by using a voltage-based charge pump or a triple modular redundant (TMR) voted voltage-controlled oscillator (VCO). A more comprehensive approach is to harden by triplication and voting (TMR) all the digital pieces (primarily the divider) of a frequency synthesis PLL, but this still leaves room for errors in the VCO and the loop filter. Instead of hardening or voting pieces of a system, such as a frequency synthesis system (i.e., clock multiplier), we will show how the entire system can be voted. There are two main ways of doing this, each with advantages and drawbacks. We will show how each has advantages in certain areas, depending on the lock acquisition and tracking characteristics of the PLL. Because of this dependency on PLL characteristics, we will briefly revisit the theory of PLLs. But first we will describe the characteristics of voters and their correct application, as some literature does not follow the voting procedure that guarantees elimination of errors. Additionally, we will find that voting clocks is a bit trickier than voting data where an infallible clock is assumed. It is our job here to produce (or recover) that assumed infallible clock!

Shuler, Robert L., Jr.↗
NASA NTRS1974

Synthesis and evaluation of phase detectors for active bit synchronizers

Self-synchronizing digital data communication systems usually use active or phase-locked loop (PLL) bit synchronizers. The three main elements of PLL synchronizers are the phase detector, loop filter, and the voltage controlled oscillator. Of these three elements, phase detector synthesis is the main source of difficulty, particularly when the received signals are demodulated square-wave signals. A phase detector synthesis technique is reviewed that provides a physically realizable design for bit synchronizer phase detectors. The development is based upon nonlinear recursive estimation methods. The phase detector portion of the algorithm is isolated and analyzed.

Mcbride, A. L.↗
NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

Gwaltney, David A.↗
NASA NTRS2013

Improved Spacecraft Tracking and Navigation Using a Portable Radio Science Receiver

The Portable Radio Science Receiver (PRSR) is a suitcase-sized open-loop digital receiver designed to be small and easy to transport so that it can be deployed quickly and easily anywhere in the world. The PRSR digitizes, downconverts, and filters using custom hardware, firmware, and software. Up to 16 channels can be independently configured and recorded with a total data rate of up to 256 Mbps. The design and implementation of the system's hardware, firmware, and software is described. To minimize costs and time to deployment, our design leveraged elements of the hardware, firmware, and software designs from the existing full-sized operational (non-portable) Radio Science Receivers (RSR) and Wideband VLBI Science Receivers (WVSR), which have successfully supported flagship NASA deep space missions at all Deep Space Network (DSN) sites. We discuss a demonstration of the PRSR using VLBI, with one part per billion angular resolution: 1 nano-radian / 200 ?as synthesized beam. This is the highest resolution astronomical instrument ever operated solely from the Southern Hemisphere. Preliminary results from two sites are presented, including the European Space Agency (ESA) sites at Cebreros, Spain and Malargue, Argentina. Malargue's South American location is of special interest because it greatly improves the geometric coverage for spacecraft navigation in the Southern Hemisphere and will for the first time provide coverage to the 1/4 of the range of declination that has been excluded from reference frame work at Ka-band.

Delta Differential One-Way (DOR)↗
NASA NTRS1993

Suppressing Transients In Digital Phase-Locked Loops

Loop of arbitrary order starts in steady-state lock. Method for initializing variables of digital phase-locked loop reduces or eliminates transients in phase and frequency typically occurring during acquisition of lock on signal or when changes made in values of loop-filter parameters called "loop constants". Enables direct acquisition by third-order loop without prior acquisition by second-order loop of greater bandwidth, and eliminates those perturbations in phase and frequency lock occurring when loop constants changed by arbitrarily large amounts.

Thomas, J. B.↗
NASA NTRS2006

Increasing Efficiency at the NTF by Optimizing Model AoA Positioning

The National Transonic Facility (NTF) at NASA Langley Research Center (LaRC) is a national resource for aeronautical research and development. The government, military and private industries rely on the capability of this facility for realistic flight data. Reducing the operation costs and keeping the NTF affordable is essential for aeronautics research. The NTF is undertaking an effort to reduce the time between data points during a pitch polar. This reduction is being driven by the operating costs of a cryogenic facility. If the time per data point can be reduced, a substantial cost savings can be realized from a reduction in liquid nitrogen (LN2) consumption. It is known that angle-of-attack (AoA) positioning is the longest lead-time item between points. In January 2005 a test was conducted at the NTF to determine the cause of the long lead-time so that an effort could be made to improve efficiency. The AoA signal at the NTF originates from onboard instrumentation then travels through a number of different systems including the signal conditioner, digital voltmeter, and the data system where the AoA angle is calculated. It is then fed into a closed loop control system that sets the model position. Each process along this path adds to the time per data point affecting the efficiency of the data taking process. Due to the nature of the closed loop feed back AoA control and the signal path, it takes approximately 18 seconds to take one pitch pause point with a typical AoA increment. Options are being investigated to reduce the time delay between points by modifying the signal path. These options include: reduced signal filtering, using analog channels instead of a digital volt meter (DVM), re-routing the signal directly to the AoA control computer and implementing new control algorithms. Each of these has potential to reduce the positioning time and together the savings could be significant. These timesaving efforts are essential but must be weighed against possible loss of data quality. For example, a reduction in filtering can introduce noise into the signal and using analog channels could result in some loss of accuracy. Data quality assessments need to be performed concurrently with timesaving techniques since data quality parameters are essential in maintaining facility integrity. This paper will highlight time saving efforts being undertaken or studied at the NTF. It will outline the instrumentation and computer systems involved in setting of the model pitch attitude then suggest changes to the process and discuss how these system changes would effect the time between data points. It also discusses the issue of data quality and how the potential efficiency changes in the system could affect it. Lastly, it will discuss the possibility of using an open loop control system and give some pros and cons of this method.

Crawford, Bradley L.↗
DOE OSTI2026

SuperLab 2.0 Showcase: Connecting Five Labs to Tackle Grid Complexity and Unlock Unique Grid Asset Potential

SuperLab 2.0 (5-Lab Demo) is a collaborative, national-scale experiment showcasing the coordination of geographically distributed energy assets in real time. The demonstration integrates 25 physical and digital assets, spanning wind, PV, batteries, electrolyzers, DC fast chargers, microgrid controllers, building automation systems, small modular reactor (SMR), control centers, and gas turbines, across five DOE national laboratories-NLR, INL, NETL, LBNL, and SNL. These assets are unified using Energy Sciences Network (ESnet), a low-latency, high-performance U.S. Department of Energy's (DOE) network, and controlled via a centralized energy controller hosted at NLR's ARIES facility. The demonstration validates the ability to stress-test hybrid energy systems under dynamic scenarios to de-risk advanced control strategies for greater resilience and flexibility. SuperLab 2.0 (5-Lab Demo) showcased a major advancement in federated national laboratory collaboration, enabling real-time, cross-laboratory experimentation to coordinate geographically dispersed distributed energy resources (DERs) using various communication protocols and networks. SuperLab 2.0 (5-Lab Demo) built on previous demonstrations conducted between NLR-PNNL and NLR-INL connecting diverse assets including distant protection devices, a SMR simulator, and a high temperature electrolyzer (HTE). Previous demos were based on a single connection between two labs with minimal coordination challenges. The 5-Lab demo with a centralized controller, distributed testbeds across different geographical locations, and use of protocols-based communication represents a scenario closer to real-world grid operations that coordinate resources across a region to meet system needs. This experiment studied how local DER controllers interact with a centralized energy controller during normal and abnormal events to maintain reliability. The SuperLab team across the five labs implemented a notional power system model equivalent of transmission and distribution lines, represented by the data networks interconnecting the labs. Each lab continuously exchanged local parameters (such as P and Q) from its Hardware-In-Loop (CHIL) and Power Hardware-In-Loop (PHIL) assets through centralized energy controller at NLR, enabling real-time interaction and coordination across sites. By leveraging ESnet as the communication backbone, the team successfully operated the distributed assets as a unified power system, with each bus represented by a different laboratory. This setup mirrors how assets interact in real-world power systems across dispersed locations with various protocols and latencies. At each lab site, assets were operated using their own local controllers which were coordinated through an overarching operation and control layer of centralized energy controller, equivalent to how an energy management system (EMS) orchestrates assets across a regional or national grid. SuperLab's federated connectivity utilized a Digital Real-Time Simulators (DRTS)-type gateway to connect Controller Hardware-In-Loop (CHIL) and PHIL assets between labs. To enable this federated connection through ESnet, a deterministic network was established where latency variations were consistent. This consistency allowed the development of digital filters for the power system assets across CHIL and PHIL interfaces to avoid unstable and unreliable grid conditions. This report provides an overview of the cross-laboratory configuration and offers insights into interconnecting geographically distributed research assets to test them as if they were co-located. This experiment represents a step toward linking nine DOE national laboratories, enabling nation-wide simulations that can address utility-driven challenges with grid resilience, flexibility, and modernization.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1980

Aliasing filter for multirate systems

Rolloff filter is inexpensive way of reducing aliasing in digital control systems. Rolloff filter operating at faster sample rate (or rates) of system with 2:1 rate ratio gives infinite attenuation at half-sample rate of fast-rate loop. Tested successfully on Space Shuttle primary flight-control systems, filter technique could be applied to other multirate sampled-data systems.

Lee, J. F. L.↗
NASA NTRS1991

Suppressed carrier full-spectrum combining

A technique to accomplish full spectrum arraying where all the telemetry power is put into the subcarrier sidebands (suppressed carrier) is described. The matched filter needed in each antenna prior to cross correlation for deriving the coherence delay and phase offsets is an open loop version of the telemetry phase lock loop provided in the Advanced Digital Receiver. In analogy with a Costas loop telemetry receiver, a squaring loss is derived, and a signal to noise ratio for the cross correlation loop phase is presented.

Rogstad, D. H.↗
NASA NTRS1972

A simple second-order digital phase-locked loop.

A simple second-order digital phase-locked loop has been designed for the Viking Orbiter 1975 command system. Excluding analog-to-digital conversion, implementation of the loop requires only an adder/subtractor, two registers, and a correctable counter with control logic. The loop considers only the polarity of phase error and corrects system clocks according to a filtered sequence of this polarity. The loop is insensitive to input gain variation, and therefore offers the advantage of stable performance over long life. Predictable performance is guaranteed by extreme reliability of acquisition, yet in the steady state the loop produces only a slight degradation with respect to analog loop performance.

Tegnelia, C. R.↗
NASA NTRS1989

Improving Estimates Of Phase Parameters When Amplitude Fluctuates

Adaptive inverse filter applied to incoming signal and noise. Time-varying inverse-filtering technique developed to improve digital estimate of phase of received carrier signal. Intended for use where received signal fluctuates in amplitude as well as in phase and signal tracked by digital phase-locked loop that keeps its phase error much smaller than 1 radian. Useful in navigation systems, reception of time- and frequency-standard signals, and possibly spread-spectrum communication systems.

Vilnrotter, V. A.↗