Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes
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77 NANOSCIENCE AND NANOTECHNOLOGY↗
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In Situ Observation of Domain Wall Lateral Creeping in a Ferroelectric Capacitor
As a promising candidate for next-generation nonvolatile memory devices, ferroelectric oxide films exhibit many emergent phenomena with functional applications, making understanding polarization switching and domain evolution behaviors of fundamental importance. However, tracking domain wall motion in ferroelectric oxide films with high spatial resolution remains challenging. Here, in this study, an in situ biasing approach for direct atomic-scale observations of domain nucleation and sideways motion is presented. By accurately controlling the applied electric field, the lateral translational speed of the domain wall can decrease to less than 2.2 Å s −1 , which is observable with atomic resolution STEM imaging. In situ observations on a capacitor structured PbZr 0.1 Ti 0.9 O 3 /La 0.7 Sr 0.3 MnO 3 heterojunction demonstrate the unique creeping behavior of a domain wall under a critical electric field, with the atomic structure of the creeping domain wall revealed. Moreover, the evolution of the metastable domain wall forms an elongated morphology, which contains a large proportion of charged segments. Phase-field simulations unveil the competition between gradient, elastic, and electrostatic energies that decide this unique domain wall creeping and morphology variation. This work paves the way toward a complete fundamental understanding of domain wall physics and potential modulations of domain wall properties in real devices.
36 MATERIALS SCIENCE↗
A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design
The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.
Phillips, Thomas A.↗
Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate
Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.
Phillips, Thomas A.↗
Coexistence and Interplay of Two Ferroelectric Mechanisms in Zn 1-x Mg x O
Ferroelectric materials promise exceptional attributes including low power dissipation, fast operational speeds, enhanced endurance, and superior retention to revolutionize information technology. However, the practical application of ferroelectric-semiconductor memory devices has been significantly challenged by the incompatibility of traditional perovskite oxide ferroelectrics with metal-oxide-semiconductor technology. Recent discoveries of ferroelectricity in binary oxides such as Zn 1-x Mg x O and Hf 1-x Zr x O have been a focal point of research in ferroelectric information technology. Here, this work investigates the ferroelectric properties of Zn 1-x Mg x O utilizing automated band excitation piezoresponse force microscopy. This findings reveal the coexistence of two ferroelectric subsystems within Zn 1-x Mg x O. A “fringing-ridge mechanism” of polarization switching is proposed that is characterized by initial lateral expansion of nucleation without significant propagation in depth, contradicting the conventional domain growth process observed in ferroelectrics. This unique polarization dynamics in Zn 1-x Mg x O suggests a new understanding of ferroelectric behavior, contributing to both the fundamental science of ferroelectrics and their application in information technology.
36 MATERIALS SCIENCE↗
Electrode and Microstructure Dependence of Oxygen Diffusion in Ferroelectric Hafnium Zirconium Oxide Thin Films
Hafnia-based ferroelectrics hold promise to reduce energy demand for computing by enabling compute-in-memory and as non-volatile memories. The ferroelectric phase in this material system is, in part, stabilized by oxygen vacancies. While oxygen vacancies may be a necessity for phase stability, they limit device endurance through diffusion and accumulation into conducting channels. Herein, it is shown that oxygen diffusion is spatially variable within individual grains of ferroelectric hafnium zirconium oxide (HZO). Using 18 O tracers and finite difference modeling, it is shown that grain boundaries and regions near electrode interfaces allow for relatively rapid oxygen diffusion, with values as much as 10 4 larger than the grain cores. Further, the selection of electrode material affects the diffusion coefficients across all microstructural regions. HZO films in contact with TiN electrodes result in more oxygen-deficient HZO films and higher oxygen diffusion coefficients. Tungsten electrodes result in fewer vacancies and lower diffusion coefficients. Diffusion activation energy differences between the HZO with the two electrodes is reconciled by differing populations of charged and uncharged oxygen vacancies. This insight into the local vacancy populations and diffusion pathways provides a platform for designing hafnia-based films, deposition processes, and integration strategies to reduce vacancy gradients and improve performance.
36 MATERIALS SCIENCE↗
Asymmetric Electrode Work Function Customization via Top Electrode Replacement in Ferroelectric and Field–Induced Ferroelectric Hafnium Zirconium Oxide Thin Films
Non-volatile memory device structures such as ferroelectric random-access memory and ferroelectric tunnel junctions employ switchable spontaneous polarization to hold binary states. These devices can potentially benefit from the imposition of spontaneous internal biases and their resulting effect on the polarization properties of the ferroelectric (or field-induced ferroelectric/ antiferroelectric) layer. While HfO 2 -based thin films are ideal candidates for implementation into these devices due to their scalability and silicon compatibility, the phase purity of these oxides is sensitive to the selection of electrode material, preventing incorporation of asymmetric electrode layers into such structures. Within this work, electrode replacement following post-metallization anneal processing is introduced as a route to achieve ferroelectric and field-induced ferroelectric Hf x Zr 1–x O 2 (HZO) thin films with electrode-independent phase constitutions. The effects of this process and the corresponding internal biases imposed across the HZO layers due to asymmetric work functions are investigated. It is shown that internal biases vary in magnitude in accordance with prediction based on the work functions of the replaced electrode layers and affect remanent polarization magnitudes. Accordingly, electrode replacement presents a processing route that can readily produce HZO films with spontaneous internal biases and electrode- independent phase constitutions, facilitating implementation of these ferroelectrics into the next generation device structures.
36 MATERIALS SCIENCE↗
A Perspective on ferroelectricity in hafnium oxide: Mechanisms and considerations regarding its stability and performance
Ferroelectric hafnium oxides are poised to impact a wide range of microelectronic applications owing to their superior thickness scaling of ferroelectric stability and compatibility with mainstream semiconductors and fabrication processes. For broad-scale impact, long-term performance and reliability of devices using hafnia will require knowledge of the phases present and how they vary with time and use. In this Perspective article, the importance of phases present on device performance is discussed, including the extent to which specific classes of devices can tolerate phase impurities. Following, the factors and mechanisms that are known to influence phase stability, including substituents, crystallite size, oxygen point defects, electrode chemistry, biaxial stress, and electrode capping layers, are highlighted. Herein, discussions will focus on the importance of considering both neutral and charged oxygen vacancies as stabilizing agents, the limited biaxial strain imparted to a hafnia layer by adjacent electrodes, and the strong correlation of biaxial stress with resulting polarization response. Areas needing additional research, such as the necessity for a more quantitative means to distinguish the metastable tetragonal and orthorhombic phases, quantification of oxygen vacancies, and calculation of band structures, including defect energy levels for pure hafnia and stabilized with substituents, are emphasized.
36 MATERIALS SCIENCE↗
Ferroelectric C-Axis Textured Aluminum Scandium Nitride Thin Films of 100 nm Thickness
We report on the properties of Aluminum Scandium Nitride (AlScN) thin films deposited by pulsed-DC co-sputtering. We present the impact of the nitrogen-to-argon gas ratio on the crystal growth orientation, film stress, surface roughness, scandium concentration, and deposition rate of 760-860 nm thick AlScN thin films on Ti/Pt (111). We utilize the optimized process conditions from this study to deposit thin layers of AlScN and to explore the nucleation and orientation of thin AlScN layers on Ti/Pt (111). We report on the ferroelectric properties of 100 nm thick AlScN materials.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Proceedings of the 4th Annual Workshop: Advances in Smart Materials for Aerospace Applications
The objective of the Fourth Annual Conference on Advances in Smart Materials for Aerospace Applications was to provide a forum for technical dialogue on numerous topics in the area of smart materials. The proceedings presented herein represent the technical contributions of the participants of the workshop. Topics addressed include shape memory alloys, ferroelectrics, fiber optics, finite element simulation, and active control.
Hardy, Robin C.↗
Evaluation of Data Retention and Imprint Characteristics of FRAMs Under Environmental Stresses for NASA Applications
A major reliability issue for all advanced nonvolatile memory (NVM) technology devices including FRAMs (Ferroelectric random access memories) is the data retention characteristics over extended period of time, under environmental stresses and exposure to total ionizing dose (TID) radiation effects. For this testing, 256 Kb FRAMs in 28-pin plastic DIPS, rated for industrial grade temperature range of -40 C to +85 C, were procured. These are two-transistor, two-capacitor (2T-2C) design FRAMs. In addition to data retention characteristics, the parts were also evaluated for imprint failures, which are defined as the failure of cells to change from a "preferred" state, where it has been for a significant period of time to an opposite state (e.g., from 1 to 0, or 0 to 1). These 256 K FRAMs were subjected to scanning acoustic microscopy (C-SAM); 1,000 temperature cycles from -65 C to +150 C; high temperature aging at 150 C, 175 C, and 200 C for 1,000 hours; highly accelerated stress test (HAST) for 500 hours; 1,000 hours of operational life test at 125 C; and total ionizing dose radiation testing. As a preconditioning, 10 K read/write cycles were performed on all devices. Interim electrical measurements were performed throughout this characterization, including special imprint testing and final electrical testing. Some failures were observed during high temperature aging test at 200 C, during HAST testing, and during 1,000 hours of operational life at 125 C. The parts passed 10 Krad exposure, but began showing power supply current increases during the dose increment from 10 Krad to 30 Krad, and at 40 Krad severe data retention and parametric failures were observed. Failures from various environmental group testing are currently being analyzed.
Sharma, Ashok K.↗
Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications
In this study, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.
97 MATHEMATICS AND COMPUTING↗
Nonvolatile memory cells from hafnium zirconium oxide ferroelectric tunnel junctions using Nb and NbN electrodes
Ferroelectric tunnel junctions (FTJs) utilizing hafnium zirconium oxide (HZO) have attracted interest as non-volatile memory for microelectronics due to ease of integration into back-end-of-line (BEOL) complementary metal oxide semiconductor fabrication. This work examines asymmetric electrode NbN/HZO/Nb devices with 7 nm thick HZO as FTJs in a memory structure, with an output resistance that can be controlled by read and write voltages. The individual FTJs are measured to have a tunneling electroresistance of 10 during the read state without significant filament conduction formation and reasonable ferroelectric performance. Endurance and remanent polarizations of up to 10 5 cycles and 20 μC/cm 2 , respectively, are measured and are shown to be dependent on the cycling voltage. Electrical measurements demonstrate how magnitude of the write pulse can modulate the high state resistance and the read pulse influences both resistance values as well as separation of resistance states. Then, by using two opposite switching FTJ devices in series, a programmable nonvolatile resistor divider is demonstrated. Measurements of these two FTJ unit memory cells show wide applicability to a BEOL microfabrication process for a re-readable, rewritable, and nonvolatile memory cell.
42 ENGINEERING↗
Analog Nonvolatile Computer Memory Circuits
In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.
MacLeod, Todd↗
One Nanometer HfO[subscript 2]-Based Ferroelectric Tunnel Junctions on Silicon
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Cheema, Suraj S.↗
Embedding security into ferroelectric FET array via in situ memory operation
Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128 × 128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows ~22.6×/~14.1× increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes.
47 OTHER INSTRUMENTATION↗
Machine Learning Reveals Memory of the Parent Phases in Ferroelectric Relaxors Ba(Ti$_{1-x}$,Zr x )O 3
Machine learning has been establishing its potential in multiple areas of condensed matter physics and materials science. Here, in this work, an unsupervised machine learning workflow is developed and used within a framework of first-principles-based atomistic simulations to investigate phases, phase transitions, and their structural origins in ferroelectric relaxors, Ba(Ti 1-x ,Zr x )O 3 . The applicability of the workflow is first demonstrated to identify phases and phase transitions in the parent compound, a prototypical ferroelectric BaTiO 3 . Then the workflow is applied for Ba(Ti 1-x ,Zrx)O 3 with x ≤ 0.25 to reveal i) that some of the compounds bear a subtle memory of BaTiO 3 phases beyond the point of the pinched phase transition, which could contribute to their enhanced electromechanical response; ii) the existence of peculiar phases with delocalized precursors of nanodomains—likely candidates for the controversial polar nanoregions; and iii) nanodomain phases for the largest concentrations of x.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
ALD-Derived WO 3– x Leads to Nearly Wake-Up-Free Ferroelectric Hf 0.5 Zr 0.5 O 2 at Elevated Temperatures
Breaking the memory wall in advanced computing architectures will require complex 3D integration of emerging memory materials such as ferroelectrics─either within the back-end-of-line (BEOL) of CMOS front-end processes or through advanced 3D packaging technologies. Achieving this integration demands that memory materials exhibit high thermal resilience, with the capability to operate reliably at elevated temperatures, such as 125°C, due to the substantial heat generated by front-end transistors. However, silicon-compatible HfO 2 -based ferroelectrics tend to exhibit antiferroelectric-like behavior in this temperature range, accompanied by a more pronounced wake-up effect, posing significant challenges to their thermal reliability. Here, we report that by introducing a thin tungsten oxide (WO 3–x ) layer─known as an oxygen reservoir─and carefully tuning its oxygen content, ultrathin Hf 0.5 Zr 0.5 O 2 (5 nm) films can be made robust against the ferroelectric-to-antiferroelectric transition at elevated temperatures. This approach not only minimizes polarization loss in the pristine state but also effectively suppresses the wake-up effect, reducing the required wake-up cycles from 10 5 to only 10 at 125°C, a qualifying temperature for back-end memory integrated with front-end logic, as defined by the JEDEC standard. First-principles density functional theory (DFT) calculations reveal that WO 3 enhances the stability of the ferroelectric orthorhombic phase (o-phase) at elevated temperatures by increasing the tetragonal-to-orthorhombic phase energy gap and promoting favorable phonon mode evolution, thereby supporting o-phase formation under both thermodynamic and kinetic constraints.
36 MATERIALS SCIENCE↗