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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Lower Cost Renewable Nanoparticle Platform to Increases Production of Cathode Material (CRADA Final Report)

Employees of Sylvatex synthesized candidate cathode materials for lithium-ion batteries in PI’s labs and at the Molecular Foundry using sustainable methods. They then benchmarked the synthesized materials against available commercial cathode materials in lithium half-cells (coin cell configurations) to compare performance and ensure that their materials met or exceeded metrics of the commercial materials.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Fabrication and Testing of Solid-Solution Strengthened Corrosion Resistant Alloys For Service in Molten Fluoride Environments

The demand for higher system thermal efficiencies requires the operation of power generation cycles and heat conversion systems at progressively higher temperatures. As the system operating temperature increases, existing materials may not provide adequate mechanical properties or environmental compatibility or both. There is an increasing commercial interest in the development and deployment of liquid-fueled Molten Salt Reactors (MSRs). Hastelloy®N, the highest performing candidate MSR structural alloy, is not capable of operations at temperatures above 700°C, thus limiting the performance of these systems. Using an Integrated Computational Materials Engineering (ICME)-approach and small laboratory scale heats, ORNL developed a class of patented alloys covered by U.S. Patent 9, 435, 011 B2, “Creep-resistant, Cobalt-free alloys for high temperature, liquid-salt heat exchanger systems,” similar to Hastelloy®N in that they are primarily solid solution strengthened. In contrast to precipitation strengthened alloys, the microstructure of solid solution alloys and hence the high temperature mechanical properties are stable for extended periods of time allowing long reactor operating life. The new alloys have shown to possess good resistance to liquid fluorides at temperatures up to 850°C and have significantly improved creep properties when compared to Hastelloy®N. The purpose of the CRADA project was for ORNL to collaborate with Haynes International- a materials producer, MetalTek International- a foundry, and Kairos Power – an advanced reactor developer – to scale-up selected alloys, evaluate their properties, and identify one solid solution strengthened alloy that can meet the property requirements for the reactor being developed by Kairos Power and other similar liquid fluoride-salt cooled reactors. As part of the project, eight alloys were down-selected and fabricated in larger industrial scale heats by Haynes International. Resistance to molten salt was evaluated in flowing FLiNaK and FLiBe by Kairos Power using their Rotating Cage Loop (RCL) system. Accounting for iron deposition during these tests, the new alloys displayed very low net mass change showing excellent corrosion performance in molten salt. Creep properties evaluated at ORNL were found to be better than that of Hastelloy®N and 316 stainless steel. Long-term stabilities of the alloys evaluated by Haynes International showed that these alloys have excellent thermal stability in the temperature range 704.4-815.6°C, with the change in strength and ductility being less than 10-15% after a 4000-hour exposure at 815.6°C. Autogenously Gas Tungsten Arc Welding (GTAW) welded samples showed less than 10% change in yield strength / ultimate tensile strength / total elongation compared to the basemetal, indicating that the alloys have excellent weldability. Three parts were successfully investment-cast using one alloy with very little voiding showing feasibility of fabricating parts using the casting process. This project enabled extensive interaction between the material producer Haynes International, casting supplier MetalTek, and reactor developer Kairos Power. This facilitated testing of materials and components produced using the newly developed alloys by the end-user. This allowed the generation of critical dataset required for down-selection of a few promising alloys for further development. This data is also currently being shared with other reactor designers for them to evaluate the suitability of this alloy for their reactor design. The availability of this alloy will ultimately enable the design and development and deployment of MSRs with increased temperature of operation and thus, improved efficiencies.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2024

Best of Both Worlds: Integrating Slurm with Kubernetes in a Kubernetes Native Way

We present K-Foundry, a framework that enables the integration of Simple Linux Utility for Resource Management (SLURM) with Kubernetes (K8s) via a Kubernetes-like Control Plane (KCP). Our implementation seamlessly enables a unified communication and scheduling layer for a fleet of multiple diverse computing platforms. While SLURM and K8s traditionally support distinct scheduling models, they have recently started aligning their objectives by moving towards a more converged execution environment.

Beltre, Angel Manuel↗
DOE OSTI2025

Fabrication and Testing of Solid-Solution Strengthened Corrosion Resistant Alloys For Service in Molten Fluoride Environments

The demand for higher system thermal efficiencies requires the operation of power generation cycles and heat conversion systems at progressively higher temperatures. As the system operating temperature increases, existing materials may not provide adequate mechanical properties or environmental compatibility or both. There is an increasing commercial interest in the development and deployment of liquid-fueled Molten Salt Reactors (MSRs). Hastelloy®N, the highest performing candidate MSR structural alloy, is not capable of operations at temperatures above 700°C, thus limiting the performance of these systems. Using an Integrated Computational Materials Engineering (ICME)-approach and small laboratory scale heats, ORNL developed a class of patented alloys covered by U.S. Patent 9,435,011 B2, “Creep-resistant, Cobalt-free alloys for high temperature, liquid-salt heat exchanger systems,” similar to Hastelloy®N in that they are primarily solid solution strengthened. In contrast to precipitation strengthened alloys, the microstructure of solid solution alloys and hence the high temperature mechanical properties are stable for extended periods of time allowing long reactor operating life. The new alloys have shown to possess good resistance to liquid fluorides at temperatures up to 850°C and have significantly improved creep properties when compared to Hastelloy®N. The purpose of the CRADA project was for ORNL to collaborate with Haynes International- a materials producer, MetalTek International- a foundry, and Kairos Power – an advanced reactor developer – to scale-up selected alloys, evaluate their properties, and identify one solid solution strengthened alloy that can meet the property requirements for the reactor being developed by Kairos Power and other similar liquid fluoride-salt cooled reactors. As part of the project, eight alloys were down-selected and fabricated in larger industrial scale heats by Haynes International. Resistance to molten salt was evaluated in flowing FLiNaK and FLiBe by Kairos Power using their Rotating Cage Loop (RCL) system. Accounting for iron deposition during these tests, the new alloys displayed very low net mass change showing excellent corrosion performance in molten salt. Creep properties evaluated at ORNL were found to be better than that of Hastelloy®N and 316 stainless steel. Long-term stabilities of the alloys evaluated by Haynes International showed that these alloys have excellent thermal stability in the temperature range 704.4-815.6°C, with the change in strength and ductility being less than 10-15% after a 4000-hour exposure at 815.6°C. Autogenously Gas Tungsten Arc Welding (GTAW) welded samples showed less than 10% change in yield strength / ultimate tensile strength / total elongation compared to the basemetal, indicating that the alloys have excellent weldability. Three parts were successfully investment-cast using one alloy with very little voiding showing feasibility of fabricating parts using the casting process. This project enabled extensive interaction between the material producer Haynes International, casting supplier MetalTek, and reactor developer Kairos Power. This facilitated testing of materials and components produced using the newly developed alloys by the end-user. This allowed the generation of critical dataset required for down-selection of a few promising alloys for further development. This data is also currently being shared with other reactor designers for them to evaluate the suitability of this alloy for their reactor design. The availability of this alloy will ultimately enable the design and development and deployment of MSRs with increased temperature of operation and thus, improved efficiencies.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Aligned carbon nanotubes for 1,000x improvement in computing (CRADA Final Report)

As part of the Cyclotron Road program, the Aligned Carbon team worked to improve and bring to market their technology to manufacture carbon nanotubes (CNTs) for integrated circuits. There are multiple applications which can benefit from the use of CNT based transistors in integrated circuits, including high performance computing, RF data transmission, and biosensing. Each of these applications faces a problem of poor starting CNT material to come to market. Aligned Carbon offers material with the highest ceiling of performance based around a fully aligned, uniform, on-wafer growth of CNTs and our proprietary purification process to remove metallic CNTs leaving only the semi-conducting ones behind. Further, Aligned Carbon has been guided by scalable manufacturing processes that will fit seamlessly into the integrated circuit foundry model of chip fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Additive Manufacturing Evaporative Casting

Traditional lost foam casting has been around for decades. The process uses foam forms blown by an injection molding like process or CNC milled into the desired shape, then pouring molten metal over the foam pattern to create a metallic object. Additive Manufacturing Evaporative Casting (AMEC) is a new process that eliminates foam forms by using additive manufacturing to 3D print the desired cast geometry. This not only saves time and money but allows for more advanced and complex designs that can’t be achieved by carving foam. Additionally, AMEC doesn’t require molds and tooling like other casting and foundry options. Because the AMEC process is new, extensive testing is needed to develop a better understanding of the process to minimize defects, quantify material properties, and start computer modeling for the process. This CRADA (collaborative research and development agreement) between ORNL and Skuld seeks to improve the process, develop a computational model, characterize material properties, and explore new applications.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production

The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the ABCStar that was reducing wafer yields in some manufactured lots from the expected 90% to as low as 2%. The root cause was determined to be a timing issue in the logic synthesized to control previously silicon proven memory blocks re-used for this ASIC. The solutions proposed included manufacturing process changes by the wafer foundry, changes to the operating parameters for the ABCStar in the detector, and the possibility that a redesign might be required. The two mitigation efforts were undertaken in parallel, with the process modification route a less desirable solution since already manufactured wafers would need to be scrapped in favour of the new ones. Based on a knowledge of the existing process, and testing done on the worst performing wafers, it was proposed that raising the core operating voltage of the ABCStar from 1.20V to 1.25V could address the timing issue by sufficiently speeding up its transistors. An extensive testing program that included the effects of temperature and radiation expected over the lifetime of the ITk detector was conducted to validate that approach. Those tests and studies proved that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required for ensuring reliable operation of the ITk. Based on testing, a further timing mitigation was implemented to provide an additional margin of reliability by increasing the duty cycle of the clock to the ABCStar. Testing of all ABCStar wafers has been completed and the production of the detector modules using these ASICs is now well underway as a result of the efforts detailed herein.

FOS: Physical sciences↗
NASA NTRS1983

Improved Gloves for Firefighters

New firefighter's gloves are more flexible and comfortable than previous designs. Since some firefighters prefer gloves made of composite materials while others prefer dip-coated gloves, both types were developed. New gloves also find uses in foundries, steelmills, and other plants where they are substituted for asbestos gloves.

Tschirch, R. P.↗
NASA NTRS1986

Ultrasonic measurement of porosity in casts and welds

The development of a quantitative nondestructive method which involves ultrasonic attenuation measurements in frequency domain to determine volume fraction of porosity in aluminum cast is discussed. The aluminum alloy A357 casting samples were produced at the Ohio State University Foundry with controlled porosity contents ranging from 0% to 6%. A computer controlled system was used to direct ultrasonic beam to a test sample to different places to conduct ultrasonic attenuation measurements. The plot of attenuation coefficients as a function of frequency was then evaluated based on existing theories to determine volume fraction of porosity and pore size.

Adler, L.↗
NASA NTRS1986

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Olson, E. M.↗
NASA NTRS1988

A CMOS matrix for extracting MOSFET parameters before and after irradiation

An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.

Blaes, B. R.↗
NASA NTRS1988

Comparison of results from simple expressions for MOSFET parameter extraction

In this paper results are compared from a parameter extraction procedure applied to the linear, saturation, and subthreshold regions for enhancement-mode MOSFETs fabricated in a 3-micron CMOS process. The results indicate that the extracted parameters differ significantly depending on the extraction algorithm and the distribution of I-V data points. It was observed that KP values vary by 30 percent, VT values differ by 50 mV, and Delta L values differ by 1 micron. Thus for acceptance of wafers from foundries and for modeling purposes, the extraction method and data point distribution must be specified. In this paper measurement and extraction procedures that will allow a consistent evaluation of measured parameters are discussed.

Buehler, M. G.↗
NASA NTRS1989

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗
NASA NTRS1989

HgCdTe 256x256 NWIR FPA

Researchers developed a HgCdTe 256x256 focal plane array (FPA) which operates in the 1 to 5 micron band. This is presently the largest demonstrated HgCdTe FPA. The detector material is HgCdTe on sapphire (PACE-1 technology) which has a low thermal expansion mismatch with silicon. The multiplexer is a CMOS FET-switch device processed through a commercial silicon foundry. The multiplexer input is direct injection and the charge capacity is about 2 times 10 to the 7th power electrons. The kTC limited read noise is 400 electrons. Researchers demonstrated high background imaging using the device. The broadband quantum efficiency is measured to be 59 percent. Dark currents less than 0.1 pA were measured at 77 K for detectors processed on PACE-1 material with 4.9 microns cutoff. The dark currents decrease as the temperature is lowered, and researchers are presently studying the T less than 77 K characteristics. The interconnect yield is greater than 95 percent. The devices are available for astronomical applications.

Vural, Kadri↗
NASA NTRS1989

Ceramic port shields cast in an iron engine head

Silicon nitride exhaust and intake port shields have been successfully cast into a gray iron cylinder head of a heavy duty diesel single cylinder research engine. Careful design considerations, finite element, and probability of survival analyses indicated viability of the design. Foundry experience, NDE, and failure investigations are reported.

Hakim, Nabil S.↗
NASA NTRS1991

Wire transfer of charge packets using a CCD-BBD structure for charge-domain signal processing

A structure for the virtual transfer of charge packets across metal wires is described theoretically and is experimentally verified. The structure is a hybrid of charge-coupled device (CCD) and bucket-brigade device (BBD) elements and permits the topological crossing of charge-domain signals in low power signal processing circuits. A test vehicle consisting of 8-, 32-, and 96-stage delay lines of various geometries implemented in a double-poly, double-metal foundry process is used to characterize the wire-transfer operation. Transfer efficiency ranging between 0.998 and 0.999 is obtained for surface n-channel devices with clock cycle times in the range from 40 ns to 0.3 ms. Transfer efficiency as high as 0.9999 is obtained for buried n-channel devices. Good agreement is found between experiment and simulation.

Fossum, Eric R.↗
NASA NTRS1994

Monolithic Optical-To-Electronic Receiver

Monolithic optoelectronic integrated circuit converts multiplexed digital optical signals into electrical signals, separates, and distributes them to intended destinations. Developed to deliver phase and amplitude commands to monolithic microwave integrated circuits (MMIC's) at elements of millimeter-wave phased-array antenna from single optical fiber driven by external array controller. Also used in distribution of high-data-rate optical communications in local-area networks (LAN's). Notable features include options for optical or electrical clock inputs; outputs for raw data, addresses, and instructions for diagnosis; and optical-signal-detection circuit used to reduce power consumption by 80 percent between data-transmission times. Chip fabricated by processes available at many major semiconductor foundries. Distribution of digital signals in aircraft, automobiles, and ships potential application.

Kunath, Richard↗
NASA NTRS1990

Assessing the SEU resistance of CMOS latches using alpha-particle sensitive test circuits

The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environment is evident in the upset rate of the Tracking and Data Relay Satellite (TDRS) launched in Apr. 1983. This satellite experiences a single-event-upset (SEU) per day which must be corrected from the ground. Such experience caused a redesign of the Galileo spacecraft with SEU resistant IC's. The solution to the SEU problem continues to be important as the complexity of spacecraft grows, the feature size of IC's decreases, and as space systems are designed with circuits fabricated at non-radiation hardened foundries. This paper describes an approach for verifying the susceptibility of CMOS latches to heavy-ion induced state changes. The approach utilizes alpha particles to induce the upsets in test circuits. These test circuits are standard cells that have offset voltages which sensitize the circuits to upsets. These results are then used to calculate the upsetability at operating voltages. In this study results are presented for the alpha particle upset of a six-transistor static random access memory (SRAM) cell. Then a methodology is described for the analysis of a standard-cell inverter latch.

Buehler, M.↗