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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Active thermal control for electronics on Mars Rovers imposes a serious penalty in weight, volume, power consumption, and reliability.
The influence of chemical and particulate contamination upon the reliability and service life of hybrid microelectronic systems is documented. Several coating systems used include the parylene and Dow Corning silicone (DC90-711). These passivating coatings have potential for decreasing the degradation caused by particulate contaminants in hybrid systems as well as the possible deleterious effect of trapping chemical contaminants which have long term degrading influences upon the performance of the system. The reliability of a representative hybrid microcircuit is enhanced by the coating process.
As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s).
The use of polymer adhesives for high reliability microcircuit applications is a radical deviation from past practices in electronic packaging. Bonding studies were performed using two gold-filled conductive adhesives, 10/90 tin/lead solder and Indalloy no. 7 solder. Various types of discrete components were mounted on ceramic substrates using both thick-film and thin-film metallization. Electrical and mechanical testing were performed on the samples before and after environmental exposure to MIL-STD-883 screening tests.
NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub-micron region. Decreasing the feature size of CMOS devices not only allows more components to be placed on a single chip, but it increases performance by allowing faster switching (or clock) speeds with reduced power compared to larger scaled devices. Higher performance, and lower operating and stand-by power characteristics of Ultra-Low Power (ULP) microelectronics are not only desirable, but also necessary to meet low power consumption design goals of critical spacecraft systems. The integration of these components in such systems, however, must be balanced with the overall risk tolerance of the project.
Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.
The rapid evolution of electronics has heralded countless benefits to humanity, enabling increases in computing power while decreasing costs. However, the constantly changing semiconductor device landscape proves to be an immense challenge for the reliability community, especially for those concerned with radiation effects on microelectronics. Changes in device manufacturing, from device structure to processing steps, may and often do change the way the device responds to radiation. While radiation hardened parts are not as much of a reliability concern, they also lag behind commercial off-the-shelf, or COTS, parts in terms of computing capabilities, some by over a decade. Many missions may have no choice but to utilize COTS. As such, these missions need to ensure their parts are reliable in the face of total ionizing dose (TID). However, part and testing facility costs limit the amount of testing possible.
Background: The self-annealing behavior of electroplated copper (Cu) at room temperature is gaining attention in the microelectronics industry due to its significant impact on reliability issues such as substrate warpage and electrical resistivity. Methods: In this study, in-situ analysis of the microstructure transition and stress relaxation of the electroplated copper upon self-annealing was conducted via synchrotron white X-ray nanodiffraction (beamline 21A, Taiwan Photon Source) and grazing-incidence X-ray diffraction (beamline 17B1, Taiwan Light Source). Significant Findings: Remarkable relaxations of deviatoric stress and absolute strain component along the [002] direction were closely related to the Cu grain growth and crystallographic reorientation at the early stage of selfannealing, and a complete stress/strain relaxation can be achieved with the cessation of microstructure transition. In conclusion, the in-situ synchrotron X-ray studies provided an insight into Cu self-annealing mechanism, offering valuable information for improving Cu interconnect reliability.
With the rapidly increasing insertion of photonic devices, circuits and subsystems into NASA spacecraft, a variety of issues associated with reliability and radiation tolerance have arisen. In this paper, we discuss these issues from the perspective of the work currently ongoing in the NASA Electronic Parts and Packaging (NEPP) Program. This Program is focused on evaluating the reliability and radiation response of advanced and emerging microelectronics and photonics technologies of interest to NASA spacecraft system designers.
Monte Carlo computer analysis method for yield and reliability predictions of integrated circuits
Chalcogenide phase change materials (PCMs) are a unique class of compounds whose switchable optical and electronic properties have fueled an explosion of emerging applications in microelectronics and microphotonics. Key to any application is the ability of PCMs to reliably switch between crystalline and amorphous states over a large number of cycles. While this issue has been extensively studied in the case of microelectronic memories, current PCM-based optical devices suffer from much inferior endurance. To understand the failure mechanisms limiting endurance of PCMs specifically in microphotonic devices, we have developed an on-chip resistive micro-heater platform and an automatic multi-modal characterization system to analyze cycling performance of optical PCMs. Reversible switching of large-area PCM devices over 50,000 cycles was demonstrated.
Herein, we have derived a gas ingress and egress equation from the first principles of ideal gases. This work is intended to benefit the hermetic microelectronics packaging community, but it may be applied to other fields that require a deep understanding of gas ingress and egress dynamics. The equation outlined herein encompasses package material properties, package characteristics, hermetic testing conditions, and service conditions. It serves as a practical utility for calculating package pressure changes due to gas ingress and egress and, therefore, a power tool for component and system service life predictions.
Understanding atomic displacement damage and propagating this understanding into validated defect-aware radiation damage models is a critical step toward achieving predictive, atoms-to-systems assessment of radiation vulnerabilities of microelectronics. These models are essential for evaluating the performance and reliability of nuclear stockpile components or space-based electronics (satellites). The goal of this project was to bridge a fundamental science gap between defect spectroscopies and atomistic modeling of radiation-induced defects on the one hand, and simulations of device response on the other hand, to develop predictive defect-aware damage models for high-fidelity device simulations of radiation-damaged III-V semiconductors.
Due to the substantial increase in power density, thermal interface resistance that can constitute more than 50% of the total thermal resistance has generally become a bottleneck for thermal management in electronics. However, conventional thermal interface materials (TIMs) such as solder, epoxy, gel, and grease cannot fulfill the requirements of electronics for high-power and long-term operation. Here, we demonstrate a high-performance TIM consisting of a heterogeneous copper-tin nanowire array, which we term 'supersolder' to emulate the role of conventional solders in bonding various surfaces. The supersolder is ultracompliant with a shear modulus 2-3 orders of magnitude lower than traditional solders and can reduce the thermal resistance by two times as compared with the state-of-the-art TIMs. This supersolder also exhibits excellent long-term reliability with >1200 thermal cycles over a wide temperature range. By resolving this critical thermal bottleneck, the supersolder enables electronic systems, ranging from microelectronics and portable electronics to massive data centers, to operate at lower temperatures with higher power density and reliability.
NLR's advanced power electronics and electric machines (APEEM) research group develops world-class experimental and modeling capabilities to design and evaluate efficient and reliable power electronics and electric machines, as well as innovative thermal management systems to maximize their performance. They also design, fabricate, and characterize advanced power electronics packaging and are developing state-of-health monitoring techniques.
Contents include the following: NASA Missions - implications to reliability and radiation constraints. Approach to Insertion of New Technologies Technology Knowledge-base development. Technology model/tool development and validation. Summary comments.
Many high-reliability systems, including space systems, use selected commercial parts (including Plastic Encapsulated Microelectronics or PEMs) for unique functionality, small size, low weight, high mechanical shock resistance, and other factors. Predominantly this usage is subjected to certain 100% tests (typically called screens) and certain destructive tests usually (but not always) performed on the flight lot (typically called qualification tests). Frequently used approaches include those documented in EEE-INST-002 and JPL DocID62212 (which are sometimes modified by the particular aerospace space systems manufacturer). In this study, approaches from these documents and several space systems manufacturers are compared to approaches from a launch systems manufacturer (SpaceX), an implantable medical electronics manufacturer (Medtronics), and a high-reliability transport system process (automotive systems). In the conclusions section, these processes are outlined for all of these cases and presented in tabular form. Then some simple comparisons are made. In this introduction section, the PEM technology qualification process is described, as documented in EEE-INST-002 (written by the Goddard Space Flight Center, GSFC), as well as the somewhat modified approach employed at the Jet Propulsion Laboratory (JPL). Approaches used at several major NASA contractors are also described
A unique miniature pressure sensor system consisting of an array of fifty integrated sensor pressure transducers with integral electronic logic and switching is described. Solid state processing of the piezoresistive array is combined with hybrid microelectronics to produce a very small, dense (80 cc displacement), high reliability pressure measuring system. Application to high speed data acquisition, energy conservation in wind tunnels and flight test is discussed. Test data are presented typifying system performance.