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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Verifying an interactive consistency circuit: A case study in the reuse of a verification technology

The work done at ORA for NASA-LRC in the design and formal verification of a hardware implementation of a scheme for attaining interactive consistency (byzantine agreement) among four microprocessors is presented in view graph form. The microprocessors used in the design are an updated version of a formally verified 32-bit, instruction-pipelined, RISC processor, MiniCayuga. The 4-processor system, which is designed under the assumption that the clocks of all the processors are synchronized, provides software control over the interactive consistency operation. Interactive consistency computation is supported as an explicit instruction on each of the microprocessors. An identical user program executing on each of the processors decides when and on what data interactive consistency must be performed. This exercise also served as a case study to investigate the effectiveness of reusing the technology which was developed during the MiniCayuga effort for verifying synchronous hardware designs. MiniCayuga was verified using the verification system Clio which was also developed at ORA. To assist in reusing this technology, a computer-aided specification and verification tool was developed. This tool specializes Clio to synchronous hardware designs and significantly reduces the tedium involved in verifying such designs. The tool is presented and how it was used to specify and verify the interactive consistency circuit is described.

Bickford, Mark↗
NASA NTRS1980

A microprocessor based high speed space-borne packet switch

The design and performance evaluation of a single microprocessor based packet switch for use on-board a satellite are presented. The primary design criterion is to maximize the system throughput. A number of protocols and their impact on the switch design are discussed. Stem and processor hardware architectures are described. The flow charts of the software required to accomplish the essential functions are presented and modification needed for use in a multisatellite network are also indicated. Maximum throughput attainable is calculated, desirable characteristics of microprocessors for this application are pointed out. A queue theoretic model of the packet switch has been developed. Analytical relationships of the average waiting times and the queue sizes at the queues and the overall average response time with the various design parameters of the switch have been obtained. A number of graphs showing the effect of variation in the number of input and output lines, data rates, destination functions, speed of output lines and some other design parameters on the performance of the switch are presented and discussed.

Arozullah, M.↗
NASA NTRS1984

A microprocessor based anti-aliasing filter for a PCM system

Described is the design and evaluation of a microprocessor based digital filter. The filter was made to investigate the feasibility of a digital replacement for the analog pre-sampling filters used in telemetry systems at the NASA Ames-Dryden Flight Research Facility (DFRF). The digital filter will utilize an Intel 2920 Analog Signal Processor (ASP) chip. Testing includes measurements of: (1) the filter frequency response and, (2) the filter signal resolution. The evaluation of the digital filter was made on the basis of circuit size, projected environmental stability and filter resolution. The 2920 based digital filter was found to meet or exceed the pre-sampling filter specifications for limited signal resolution applications.

Morrow, D. C.↗
NASA NTRS1980

G-cueing microcontroller (a microprocessor application in simulators)

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

Horattas, C. G.↗
NASA NTRS1980

A microprocessor based high speed packet switch for satellite communications

The architectures of a single processor, a three processor, and a multiple processor system are described. The hardware circuits, and software routines required for implementing the three and multiple processor designs are presented. A bit-slice microprocessor was designed and microprogrammed. Maximum throughput was calculated for all three designs. Queue theoretic models for these three designs were developed and utilized to obtain analytical expressions for the average waiting times, overall average response times and average queue sizes. From these expressions, graphs were obtained showing the effect on the system performance of a number of design parameters.

Arozullah, M.↗
NASA NTRS1992

Development of a differentially balanced magnetic bearing and control system for use with a flywheel energy storage system

The purpose of a magnetically suspended flywheel energy storage system for electric utility load leveling is to provide a means to store energy during times when energy is inexpensive to produce and then return it to the customer during times of peak power demand when generated energy is most expensive. The design of a 20 kWh flywheel energy storage system for electric utility load leveling applications involves the successful integration of a number of advanced technologies so as to minimize the size and cost of the system without affecting its efficiency and reliability. The flywheel energy storage system uses a carbon epoxy flywheel, two specially designed low loss magnetic bearings, a high efficiency motor generator, and a 60 cycle AC power converter all integrated through a microprocessor controller. The basic design is discussed of each of the components that is used in the energy storage design.

Higgins, Mark A.↗
NASA NTRS1994

Field and data analysis studies related to the atmospheric environment

This report summarizes work on a broad array of projects including: (1) applications of meteorological and/or oceanographic satellites; (2) improvement of the current set of NASA/USAF lightning related launch commit criteria rules; (3) the design, building, testing and deployment of a set of cylindrical field mills for aircraft use; (4) the study of marginal electrification storm conditions in relationship to the current launch commit rules for the space shuttle and various other launch vehicles using an instrumented aircraft; (5) support of the DC-8 and ER-2 lightning instrument package as part of both the Tropical Ocean - Global Atmospheric/Coupled Ocean-Atmospheric Response Experiment and the Convection and Moisture Experiment; (6) design of electronic circuitry and microprocessor firmware for the NASA Advanced Ground Based Field Mill; (7) design and testing of electronic and computer instrumentation for atmospheric electricity measurements; (8) simulating observations from a lightning imaging sensor on the Tropical Rainfall Measuring satellite; and (9) supporting scientific visualization and the development of computer software tools.

Kidder, Stanley↗
NASA NTRS1980

Microprocessor software applications for flight training simulators

The g cueing system software design and implementation in the dual microprocessor system of the F-15 operational flight training simulator g cueing system is presented. The software is structured in the two microcomputers such that one serves as a controller performing all logical functions and interface with the host computer system while the other serves as an arithmetic unit performing all mathematical functions.

Leavy, W. P.↗
NASA NTRS1981

Bi-directional communication interface for microprocessor-to-system/370

The design and operation of a bi-directional communication interface between a microcomputer and the IBM System/370 is documented. The hardware unit interconnects a modem to interface to the S/370, the microcomputer with an EIA I/O port, and a terminal for sending and receiving data from either the microcomputer or the S/370. Also described is the software necessary for the two-way interface. This interface is designed so that no modifications need to be made to the terminal, modem, or microcomputer.

Fischer, J. P.↗
NASA NTRS1982

Bi-directional communication interface for microprocessor-to-system/370

The design and operation of a bi-directional communication interface between a microcomputer and the IBM System/370 is documented. The hardware unit inter-connects a modem to interface to the S/370, the microcomputer with an EIA I/O port, and a terminal for sending and receiving data from either the microcomputer of the S/370. The software necessary for the two-way interface is also described. This interface was designed so that no modifications need to be made to the terminal, modem or microcomputer.

Fischer, J. P.↗
NASA NTRS1981

Human supervision and microprocessor control of an optical tracking system

Gunners using small calibre anti-aircraft systems have not been able to track high-speed air targets effectively. Substantial improvement in the accuracy of surface fire against attacking aircraft has been realized through the design of a director-type weapon control system. This system concept frees the gunner to exercise a supervisory/monitoring role while the computer takes over continuous target tracking. This change capitalizes on a key consideration of human factors engineering while increasing system accuracy. The advanced system design, which uses distributed microprocessor control, is discussed at the block diagram level and is contrasted with the previous implementation.

Bigley, W. J.↗
NASA NTRS1981

Development of a fault-tolerant microprocessor based computer system for space flight

A methodology for the design of a tightly coupled, highly reliable microprocessor based computer system is described. The concept of triple modular redundancy with sparing is used. The notion of synchronizing by using a single crystal oscillator is examined. The use of decoders to replace voters is also used. The decoders not only isolate the failed module but also allow error identification to be accomplished. Each module is to have its own RAM memory. The necessary circuitry to select a correct memory and the corresponding DMA controller was designed.

Montgomery, V. T.↗
NASA NTRS1980

A microprocessor based high speed packet switch for satellite communications, executive summary

The feasibility of using microprocessors to control satellite-borne packet switching was investigated by designing a packet switch architecture suitable for microprocessor control, using 2900 series components to design the processor(s), and evaluating the packet switch in terms of system throughput, delay, and queue sizes without the packet switch. System architecture for one, three, and multiple processors was designed and evaluated. The production cost of the single processor packet switch is estimated at $500,000, excluding cost of development. The three processor version which can support a maximum throughput of 500,000 packets/sec is estimated to have a production cost of under $100,000. For the multiple processor system, cost is believed to be proportional to throughput, with $1,000,000 for 500,000 packets/sec being the proportionality factor.

Arozullah, M.↗
NASA NTRS1984

Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

A methodology was developed a assess the upset susceptibility/reliability of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general purpose microprocessor were studied. The upset tests involved the random input of analog transients which model lightning induced signals onto interface lines of an 8080 based microcomputer from which upset error data was recorded. The program code on the microprocessor during tests is designed to exercise all of the machine cycles and memory addressing techniques implemented in the 8080 central processing unit. A statistical analysis is presented in which possible correlations are established between the probability of upset occurrence and transient signal inputs during specific processing states and operations. A stochastic upset susceptibility model for the 8080 microprocessor is presented. The susceptibility of this microprocessor to upset, once analog transients have entered the system, is determined analytically by calculating the state probabilities of the stochastic model.

Belcastro, C. M.↗
NASA NTRS1988

Lunar material transport vehicle

The proposed vehicle, the Lunar Material Transport Vehicle (LMTV), has a mission objective of efficient lunar soil material transport. The LMTV was designed to meet a required set of performance specifications while operating under a given set of constraints. The LMTV is essentially an articulated steering, double-ended dump truck. The vehicle moves on four wheels and has two identical chassis halves. Each half consists of a chassis frame, a material bucket, two wheels with integral curvilinear synchronous motors, a fuel cell and battery arrangement, an electromechanically actuated dumping mechanism, and a powerful microprocessor. The vehicle, as designed, is capable of transporting up to 200 cu ft of material over a one mile round trip per hour. The LMTV is capable of being operated from a variety of sources. The vehicle has been designed as simply as possible with attention also given to secondary usage of components.

Fisher, Charles D.↗
NASA NTRS1995

High Performance Parallel Computational Nanotechnology

At a recent press conference, NASA Administrator Dan Goldin encouraged NASA Ames Research Center to take a lead role in promoting research and development of advanced, high-performance computer technology, including nanotechnology. Manufacturers of leading-edge microprocessors currently perform large-scale simulations in the design and verification of semiconductor devices and microprocessors. Recently, the need for this intensive simulation and modeling analysis has greatly increased, due in part to the ever-increasing complexity of these devices, as well as the lessons of experiences such as the Pentium fiasco. Simulation, modeling, testing, and validation will be even more important for designing molecular computers because of the complex specification of millions of atoms, thousands of assembly steps, as well as the simulation and modeling needed to ensure reliable, robust and efficient fabrication of the molecular devices. The software for this capacity does not exist today, but it can be extrapolated from the software currently used in molecular modeling for other applications: semi-empirical methods, ab initio methods, self-consistent field methods, Hartree-Fock methods, molecular mechanics; and simulation methods for diamondoid structures. In as much as it seems clear that the application of such methods in nanotechnology will require powerful, highly powerful systems, this talk will discuss techniques and issues for performing these types of computations on parallel systems. We will describe system design issues (memory, I/O, mass storage, operating system requirements, special user interface issues, interconnects, bandwidths, and programming languages) involved in parallel methods for scalable classical, semiclassical, quantum, molecular mechanics, and continuum models; molecular nanotechnology computer-aided designs (NanoCAD) techniques; visualization using virtual reality techniques of structural models and assembly sequences; software required to control mini robotic manipulators for positional control; scalable numerical algorithms for reliability, verifications and testability. There appears no fundamental obstacle to simulating molecular compilers and molecular computers on high performance parallel computers, just as the Boeing 777 was simulated on a computer before manufacturing it.

Saini, Subhash↗
NASA NTRS1976

Programmable data collection platform study

The results of a feasibility study incorporating microprocessors in data collection platforms in described. An introduction to microcomputer hardware and software concepts is provided. The influence of microprocessor technology on the design of programmable data collection platform hardware is discussed. A standard modular PDCP design capable of meeting the design goals is proposed, and the process of developing PDCP programs is examined. A description of design and construction of the UT PDCP development system is given.

Source record↗
NASA NTRS1978

A user oriented microcomputer facility for designing linear quadratic Gaussian feedback compensators

A laboratory design facility for digital microprocessor implementation of linear-quadratic-Gaussian feedback compensators is described. Outputs from user interactive programs for solving infinite time horizon LQ regulator and Kalman filter problems were conditioned for implementation on the laboratory microcomputer system. The software consisted of two parts: an offline high-level program for solving the LQ Ricatti equations and generating associated feedback and filter gains and a cross compiler/macro assembler which generates object code for the target microprocessor system. A PDP 11/70 with a UNIX operating system was used for all high level program and data management, and the target microprocessor system is an Intel MDS (8080-based processor). Application to the control of a two dimensional inverted pendulum is presented and issues in expanding the design/prototyping system to other target machine architectures are discussed.

Houpt, P. K.↗