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At least 73 records · Page 4

A report of work activities on the NASA Spacelink public electronic library

NASA Spacelink is a comprehensive electronic data base of NASA and other source educational and informational materials. This service originates at Marshall Space Flight Center (MSFC) in Huntsville, Alabama. This is an education service of NASA Headquarters, through the MSFC Education Office, that first began in February of 1988. The new NASA Spacelink Public Electronic Library was the result of a study conducted to investigate an upgrade or redesign of the original NASA Spacelink. The UNIX Operating System was chosen to be the host operating system for the new NASA Spacelink Public Electronic Library. The UNIX system was selected for this project because of the strengths built into the embedded communication system and for its simple and direct file handling capabilities. The host hardware of the new system is a Sun Microsystems SPARCserver 1000 computer system. The configuration has four 50-MHz SuperSPARC processors with 128 megabytes of shared memory; three SB800 serial ports allowing 24 cable links for phone communications; 4.1 gigabytes of on-line disk storage; and ten (10) CD-ROM drives. Communications devices on the system are sufficient to support the expected number of users through the Internet, the local dial services, long distance dial services; the MSFC PABX, and the NPSS (NASA Packet Switching System) and 1-800 access service for the registered teachers.

Smith, Willard A.↗

A study of workstation computational performance for real-time flight simulation

With recent advances in microprocessor technology, some have suggested that modern workstations provide enough computational power to properly operate a real-time simulation. This paper presents the results of a computational benchmark, based on actual real-time flight simulation code used at Langley Research Center, which was executed on various workstation-class machines. The benchmark was executed on different machines from several companies including: CONVEX Computer Corporation, Cray Research, Digital Equipment Corporation, Hewlett-Packard, Intel, International Business Machines, Silicon Graphics, and Sun Microsystems. The machines are compared by their execution speed, computational accuracy, and porting effort. The results of this study show that the raw computational power needed for real-time simulation is now offered by workstations.

Maddalon, Jeffrey M.↗

Single crystal silicon filaments fabricated in SOI: A potential IR source for a microfabricated photometric CO2 sensor

The objective of this project was to design, fabricate, and test single crystal silicon filaments as potential black body IR sources for a spectrophotometric CO2 sensing microsystem. The design and fabrication of the silicon-on-insulator (SOI) filaments are summarized and figures showing the composite layout of the filament die (which contains four filaments of different lengths -- 500 microns, 1 mm, 1.5 mm and 2 mm -- and equal widths of 15 microns) are presented. The composite includes four mask layers: (1) silicon - defines the filament dimensions and contact pads; (2) release pit - defines the oxide removed from under the filament and hence, the length of the released filament; (3) Pyrex pit - defines the pit etched in the Pyrex cap (not used); and (4) metal - defines a metal pattern on the contact pads or used as a contact hole etch. I/V characteristics testing of the fabricated SOI filaments is described along with the nitride-coating procedures carried out to prevent oxidation and resistance instability.

Tu, Juliana↗

UNIX-based operating systems robustness evaluation

Robust operating systems are required for reliable computing. Techniques for robustness evaluation of operating systems not only enhance the understanding of the reliability of computer systems, but also provide valuable feed- back to system designers. This thesis presents results from robustness evaluation experiments on five UNIX-based operating systems, which include Digital Equipment's OSF/l, Hewlett Packard's HP-UX, Sun Microsystems' Solaris and SunOS, and Silicon Graphics' IRIX. Three sets of experiments were performed. The methodology for evaluation tested (1) the exception handling mechanism, (2) system resource management, and (3) system capacity under high workload stress. An exception generator was used to evaluate the exception handling mechanism of the operating systems. Results included exit status of the exception generator and the system state. Resource management techniques used by individual operating systems were tested using programs designed to usurp system resources such as physical memory and process slots. Finally, the workload stress testing evaluated the effect of the workload on system performance by running a synthetic workload and recording the response time of local and remote user requests. Moderate to severe performance degradations were observed on the systems under stress.

Chang, Yu-Ming↗

Petabyte Class Storage at Jefferson Lab (CEBAF)

By 1997, the Thomas Jefferson National Accelerator Facility will collect over one Terabyte of raw information per day of Accelerator operation from three concurrently operating Experimental Halls. When post-processing is included, roughly 250 TB of raw and formatted experimental data will be generated each year. By the year 2000, a total of one Petabyte will be stored on-line. Critical to the experimental program at Jefferson Lab (JLab) is the networking and computational capability to collect, store, retrieve, and reconstruct data on this scale. The design criteria include support of a raw data stream of 10-12 MB/second from Experimental Hall B, which will operate the CEBAF (Continuous Electron Beam Accelerator Facility) Large Acceptance Spectrometer (CLAS). Keeping up with this data stream implies design strategies that provide storage guarantees during accelerator operation, minimize the number of times data is buffered allow seamless access to specific data sets for the researcher, synchronize data retrievals with the scheduling of postprocessing calculations on the data reconstruction CPU farms, as well as support the site capability to perform data reconstruction and reduction at the same overall rate at which new data is being collected. The current implementation employs state-of-the-art StorageTek Redwood tape drives and robotics library integrated with the Open Storage Manager (OSM) Hierarchical Storage Management software (Computer Associates, International), the use of Fibre Channel RAID disks dual-ported between Sun Microsystems SMP servers, and a network-based interface to a 10,000 SPECint92 data processing CPU farm. Issues of efficiency, scalability, and manageability will become critical to meet the year 2000 requirements for a Petabyte of near-line storage interfaced to over 30,000 SPECint92 of data processing power.

Chambers, Rita↗

Low volume packaging for a microinstrumentation system

A folding, multi-platform assembly has been developed for the packaging of a multi-chip microinstrumentation system. The assembly includes three solid platforms connected by flexible micromachined ribbon cables and it can be populated by sensors and electronics from a variety of technologies including surface mount and integrated circuit (IC) processes. The entire structure is fabricated from a four-inch silicon wafer using a simple four mask process and a post-process EDP etch. The micromachined ribbon cables allow the platform assembly to be folded into a three level structure with control electronics on the bottom level, microsensors and interface electronics on the second level, and sensors that need environmental access on the top level. Using the silicon multi-platform assembly, a prototype microinstrumentation system has been developed that includes a microcontroller unit and sensors for measuring temperature, barometric pressure, humidity, altitude, and acceleration as well as a telemetry device for wireless communication. When folded in the three level structure, this microsystem occupies only 5 cc and can be placed in an outer case the size of a wristwatch.

Mason, A.↗

Pyroelectric Applications of the VDF-TrFE Copolymer

VDF/TrFe pyroelectric sensors have now definitely reached the level of a product. Based on a bidimensional staring array, it can be considered as a whole system with a monolithic technology processed on a silicon substrate provided with the integrated read out circuit. The paper will describe the main procedure dealing with the elaboration of a 32 x 32 focal plane array developed, in the context of the PROMETHEUS PROCHIP European Program (EUREKA), as a passive infrared obstacle detection applied to automotive. Additional experimental data suggest that this microsystem could operate in space environment.

Simonne, J. J.↗

Regular Topologies for Gigabit Wide-Area Networks: Congestion Avoidance Testbed Experiments

This document is Volume 3 of the final technical report on the work performed by SRI International (SRI) on SRI Project 8600. The document includes source listings for all software developed by SRI under this effort. Since some of our work involved the use of ST-II and the Sun Microsystems, Inc. (Sun) High-Speed Serial Interface (HSI/S) driver, we have included some of the source developed by LBL and BBN as well. In most cases, our decision to include source developed by other contractors depended on whether it was necessary to modify the original code. If we have modified the software in any way, it is included in this document. In the case of the Traffic Generator (TG), however, we have included all the ST-II software, even though BBN performed the integration, because the ST-II software is part of the standard TG release. It is important to note that all the code developed by other contractors is in the public domain, so that all software developed under this effort can be re-created from the source included here.

Denny, Barbara A.↗

ACTS 118x Final Report High-Speed TCP Interoperability Testing

With the recent explosion of the Internet and the enormous business opportunities available to communication system providers, great interest has developed in improving the efficiency of data transfer using the Transmission Control Protocol (TCP) of the Internet Protocol (IP) suite. The satellite system providers are interested in solving TCP efficiency problems associated with long delays and error-prone links. Similarly, the terrestrial community is interested in solving TCP problems over high-bandwidth links. Whereas the wireless community is interested in improving TCP performance over bandwidth constrained, error-prone links. NASA realized that solutions had already been proposed for most of the problems associated with efficient data transfer over large bandwidth-delay links (which include satellite links). The solutions are detailed in various Internet Engineering Task Force (IETF) Request for Comments (RFCs). Unfortunately, most of these solutions had not been tested at high-speed (155+ Mbps). Therefore, the NASA's ACTS experiments program initiated a series of TCP experiments to demonstrate scalability of TCP/IP and determine how far the protocol can be optimized over a 622 Mbps satellite link. These experiments were known as the 118i and 118j experiments. During the 118i and 118j experiments, NASA worked closely with SUN Microsystems and FORE Systems to improve the operating system, TCP stacks. and network interface cards and drivers. We were able to obtain instantaneous data throughput rates of greater than 520 Mbps and average throughput rates of 470 Mbps using TCP over Asynchronous Transfer Mode (ATM) over a 622 Mbps Synchronous Optical Network (SONET) OC12 link. Following the success of these experiments and the successful government/industry collaboration, a new series of experiments. the 118x experiments. were developed.

Ivancic, William D.↗

Deep Space Systems Technology Program Future Deliveries

NASA is in a period of frequent launches of low cost deep space missions with challenging performance needs. The modest budgets of these missions make it impossible for each to develop its own technology, therefore, efficient and effective development and insertion of technology for these missions must be approached at a higher level than has been done in the past. The Deep Space Systems Technology Program (DSST), often referred to as X2000, has been formed to address this need. The program is divided into a series of "Deliveries" that develop and demonstrate a set of spacecraft system capabilities with broad applicability for use by multiple missions. The First Delivery Project, to be completed in 2001, will provide a one MRAD-tolerant flight computer, power switching electronics, efficient radioisotope power source, and a transponder with services at 8.4 GHz and 32 GHz bands. Plans call for a Second Delivery in late 2003 to enable complete deep space systems in the 10 to 50 kg class, and a Third Delivery built around Systems on a Chip (extreme levels of electronic and microsystems integration) around 2006. Formulation of Future Deliveries (past the First Delivery) is ongoing and includes plans for such developments as highly miniaturized digital/analog/power electronics, optical communications, multifunctional structures, miniature lightweight propulsion, advanced thermal control techniques, highly efficient radioisotope power sources, and a unified flight ground software architecture to support the needs of future highly intelligent space systems. All developments are targeted at broad applicability and reuse, and will be commercialized within the US.

Salvo, Christopher G.↗

NASA's 3D Flight Computer for Space Applications

The New Millennium Program (NMP) Integrated Product Development Team (IPDT) for Microelectronics Systems was planning to validate a newly developed 3D Flight Computer system on its first deep-space flight, DS1, launched in October 1998. This computer, developed in the 1995-97 time frame, contains many new computer technologies previously never used in deep-space systems. They include: advanced 3D packaging architecture for future low-mass and low-volume avionics systems; high-density 3D packaged chip-stacks for both volatile and non-volatile mass memory: 400 Mbytes of local DRAM memory, and 128 Mbytes of Flash memory; high-bandwidth Peripheral Component Interface (Per) local-bus with a bridge to VME; high-bandwidth (20 Mbps) fiber-optic serial bus; and other attributes, such as standard support for Design for Testability (DFT). Even though this computer system did not complete on time for delivery to the DS1 project, it was an important development along a technology roadmap towards highly integrated and highly miniaturized avionics systems for deep-space applications. This continued technology development is now being performed by NASA's Deep Space System Development Program (also known as X2000) and within JPL's Center for Integrated Space Microsystems (CISM).

Alkalai, Leon↗

NASA/University JOint VEnture (JOVE) Program. VIXEN(tm): Object-Oriented, Technology-Adaptive, Virtual Information Exchange Environment

Vixen is a collection of enabling technologies for uninhibited distributed object computing. In the Spring of 1995 when Vixen was proposed, it was an innovative idea very much ahead of its time. But today the technologies proposed in Vixen have become standard technologies for Enterprise Computing. Sun Microsystems J2EE/EJB specifications, among others, are independently proposed technologies of the Vixen type. I have brought Vixen completely under the J2EE standard in order to maximize interoperability and compatibility with other computing industry efforts. Vixen and the Enterprise JavaBean (EJB) Server technologies are now practically identical; OIL, another Vixen technology, and the Java Messaging System (JMS) are practically identical; and so on. There is no longer anything novel or patentable in the Vixen work performed under this grant. The above discussion, notwithstanding, my independent development of Vixen has significantly helped me, my university, my students and the local community. The undergraduate students who worked with me in developing Vixen have enhanced their expertise in what has become the cutting edge technology of their industry and are therefore well positioned for lucrative employment opportunities in the industry. My academic department has gained a new course: "Multi-media System Development", which provides a highly desirable expertise to our students for employment in any enterprise today. The many Outreach Programs that I conducted during this grant period have exposed local Middle School students to the contributions that NASA is making in our society as well as awakened desires in many such students for careers in Science and Technology. I have applied Vixen to the development of two software packages: (a) JAS: Joshua Application Server - which allows a user to configure an EJB Server to serve a J2EE compliant application over the world wide web; (b) PCM: Professor Course Manager: a J2EE compliant application for configuring a course for distance learning. These types of applications are, however, generally available in the industry today.

Anyiwo, Joshua C.↗

Thin Film Li Ion Microbatteries for NASA Applications

Rechargeable thin film microbatteries have recently become the topic of widespread research for use in low power applications such as battery-backed CMOS memory, miniaturized implantable medical devices and smart cards. In particular, the Center for Integrated Space Microsystems (CISM) at NASA's Jet Propulsion Laboratory has interest in applying this technology for secondary power systems in miniaturized satellites, microsensors, microactuators and other remote MEMS applications. The general requirements of the microbatteries for these applications are high specific energy, wide range of temperature stability. low self-discharge rate, and flexibility of cell design. The thin film Li ion materials system using LiCoO2(LiPO(x)N(1-x))SnO is expected to fulfill these requirements.

West, W. C.↗

Electrically Isolating Subsystems in SOAC Technologies

Integrated circuit fabrication technology has evolved to the point that it is possible to construct complete systems, including power, data processing, and communications, on a single chip. Such System-on-a-chip (SOAC) technologies can enable drastic reductions in spacecraft size and weight, lowering the cost of missions and presenting new mission opportunities. This paper overviews some key enabling technologies unique to the needs of spacecraft for outer-planet exploration and missions requiring extreme resistance to radiation such as Europa orbiters and Europa Landers. The work is being carried out by Kansas State University (KSU) under direction of the Center for Integrated Space Microsystems (CISM) at NASA's Jet Propulsion Laboratory. Additional information is contained in the original extended abstract.

Boyd, R. M.↗

Integration of Passive Components for Spacecraft Avionics

The NASA roadmap outlining future deep space missions to Europa and other outer planetary destinations calls for continued reductions in the mass and volume of the spacecraft avionics. Spacecraft power electronics, including the power switches and converters, remain difficult to miniaturize due to the need for large numbers of discrete passive components such as resistors, capacitors, inductors and transformers. As part of the System-on-a-chip program at the Center for Integrated Space Microsystems and at the University of Arkansas, we are working to develop integrated or embedded passive components geared specifically for use in power management and distribution (PMAD) in future avionics over the next five to ten years. This will not only enable a scaling down of the power subsystems, but will make possible new architectures such as "distributed" PMAD. Additional information is contained in the original extended abstract.

Brandon, E. J.↗

A Multi-Mission Testbed for Advanced Technologies

The mission of the Center for Space Integrated Microsystem (CSIM) at the Jet Propulsion Laboratory is to develop advanced avionics systems for future deep space missions. The Advanced Micro Spacecraft (AMS) task is building a multi-mission testbed facility to enable the infusion of CSIM technologies into future missions. The testbed facility will also perform experimentation for advanced avionics technologies and architectures to meet challenging power, performance, mass, volume, reliability, and fault tolerance of future missions. The testbed facility has two levels of testbeds: (1) a Proof-of-Concept (POC) Testbed and (2) an Engineering Model Testbed. The methodology of the testbed development and the process of technology infusion are presented in a separate paper in this conference. This paper focuses only on the design, implementation, and application of the POC testbed. Additional information is contained in the original extended abstract.

Chau, S. N.↗

Advanced RF Front End Technology

The ability to achieve low-mass low-cost micro/nanospacecraft for Deep Space exploration requires extensive miniaturization of all subsystems. The front end of the Telecommunication subsystem is an area in which major mass (factor of 10) and volume (factor of 100) reduction can be achieved via the development of new silicon based micromachined technology and devices. Major components that make up the front end include single-pole and double-throw switches, diplexer, and solid state power amplifier. JPL's Center For Space Microsystems - System On A Chip (SOAC) Program has addressed the challenges of front end miniaturization (switches and diplexers). Our objectives were to develop the main components that comprise a communication front end and enable integration in a single module that we refer to as a 'cube'. In this paper we will provide the latest status of our Microelectromechanical System (MEMS) switches and surface micromachined filter development. Based on the significant progress achieved we can begin to provide guidelines of the proper system insertion for these emerging technologies. Additional information is contained in the original extended abstract.

Herman, M. I.↗

Ultra Low Power, Radiation Tolerant UHF Radio Technologies for In Situ Communication Applications

For future deep space missions, significant reductions in the mass and power requirements for short-range telecommunication systems will be critical in enabling a wide variety of new mission concepts. These possibilities include penetrators, gliders, miniature rovers, and sensor networks. Under joint funding from NASA's Cross Enterprise and JPL's Telecommunications and Mission technology programs, recent development activity has focused on the design of ultralow mass and power transceiver systems and subsystems suitable for operation in a flight environment. For these efforts, the functionality of the transceiver has been targeted towards a specific Mars communications scenario. However, the overall architecture is well suited to any short or medium range application where a remote probe will aperiodically communicate with a base station, possibly an orbiter, for the eventual purpose of relaying science information back to Earth. In 2001, these sponsors have been augmented with collaborative expertise and funding from JPL's Center for Integrated Space Microsystems in order to migrate existing concepts and designs to a System on a Chip (SOAC) solution. Additional information is contained in the original extended abstract.

Lay, N. E.↗