Search NASA⌕ Search

SEARCH · Search NASA

Results for “network architecture”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 73 records · Page 4

Genomics and Proteomics Based Security Protocols for Secure Network Architectures

A hardware design that integrates live and algorithmic inhabitants to produce patterns of gene expression in vivo and in silico Protocols and algorithms based upon the processes of regulation of gene expression to produce cryptographic representations of genes, RNA, proteins, and gene expression to perform authentication and confidentiality functions for computers and networks. A network concept of operations integrating all of the above into existing legacy networks.

Security Genomics↗

Neural network architectures to analyze OPAD data

A prototype Optical Plume Anomaly Detection (OPAD) system is now installed on the space shuttle main engine (SSME) Technology Test Bed (TTB) at MSFC. The OPAD system requirements dictate the need for fast, efficient data processing techniques. To address this need of the OPAD system, a study was conducted into how artificial neural networks could be used to assist in the analysis of plume spectral data.

Whitaker, Kevin W.↗

Cascaded VLSI neural network architecture for on-line learning

High-speed, analog, fully-parallel, and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A computation intensive feature classification application was demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as an application specific coprocessor for solving real world problems at extremely high data rates.

Thakoor, Anilkumar P.↗

Cascaded VLSI neural network architecture for on-line learning

High-speed, analog, fully-parallel and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware-compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A comparison-intensive feature classification application has been demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as application-specific-coprocessors for solving real-world problems at extremely high data rates.

Duong, Tuan A.↗

COTS-Based Fault Tolerance in Deep Space: Qualitative and Quantitative Analyses of a Bus Network Architecture

Using COTS products, standards and intellectual properties (IPs) for all the system and component interfaces is a crucial step toward significant reduction of both system cost and development cost as the COTS interfaces enable other COTS products and IPs to be readily accommodated by the target system architecture. With respect to the long-term survivable systems for deep-space missions, the major challenge for us is, under stringent power and mass constraints, to achieve ultra-high reliability of the system comprising COTS products and standards that are not developed for mission-critical applications. The spirit of our solution is to exploit the pertinent standard features of a COTS product to circumvent its shortcomings, though these standard features may not be originally designed for highly reliable systems. In this paper, we discuss our experiences and findings on the design of an IEEE 1394 compliant fault-tolerant COTS-based bus architecture. We first derive and qualitatively analyze a -'stacktree topology" that not only complies with IEEE 1394 but also enables the implementation of a fault-tolerant bus architecture without node redundancy. We then present a quantitative evaluation that demonstrates significant reliability improvement from the COTS-based fault tolerance.

Tai, Ann T.↗

Power, Avionics and Software Communication Network Architecture

This document describes the communication architecture for the Power, Avionics and Software (PAS) 2.0 subsystem for the Advanced Extravehicular Mobile Unit (AEMU). The following systems are described in detail: Caution Warn- ing and Control System, Informatics, Storage, Video, Audio, Communication, and Monitoring Test and Validation. This document also provides some background as well as the purpose and goals of the PAS project at Glenn Research Center (GRC).

Avionics↗

1D-Convolutional Neural Network Architecture for Generalized Time-Segmentation Tasks

Time segmentation of experimental data is a common and often difficult task. Consequently, it is of interest to automate this type of segmentation to reduce manual inputs, which are labor intensive and less consistent. However, simple thresholding algorithms are often insufficiently robust due either to noise or inconsistent data. This paper proposes a simple 1D CNN architecture as a generalized solution for typical time segmentation tasks. The layer architecture, training methods, and methods for simple customization are described as well as the results of application to three separate arc jet data streams: facility condition segmentation, video highlight segmentation, and calorimeter time-series segmentation.

Machine learning↗

1d-Convolutional Neural Network Architecture for Generalized Time-Segmentation Tasks

Time segmentation of experimental data is a common and often difficult task. Consequently, it is of interest to automate this type of segmentation to reduce manual inputs, which are labor intensive and less consistent. However, simple thresholding algorithms are often insufficiently robust due either to noise or inconsistent data. This paper proposes a simple 1D CNN architecture as a generalized solution for typical time segmentation tasks. The layer architecture, training methods, and methods for simple customization are described as well as the results of application to three separate arc jet data streams: facility condition segmentation, video highlight segmentation, and calorimeter time-series segmentation.

Machine learning↗

1D-Convolutional Neural Network Architecture for Generalized Time-Segmentation Tasks

Time segmentation of experimental data is a common and often difficult task. Consequently, it is of interest to automate this type of segmentation to reduce manual inputs, which are labor intensive and less consistent. However, simple thresholding algorithms are often insufficiently robust due either to noise or inconsistent data. This paper proposes a simple 1D convolutional neural net (CNN) architecture as a generalized solution for typical time segmentation tasks. The layer architecture, training methods, and methods for simple customization are described as well as the results of application to three separate arc jet data streams: facility condition segmentation, video highlight segmentation, and calorimeter time-series segmentation.

Machine learning↗

1D-Convolutional Neural Network Architecture for Generalized Time-series Segmentation

Time segmentation of experimental data is a common and often difficult task. Consequently, it is of interest to automate this type of segmentation to reduce manual inputs, which are labor intensive and less consistent. However, simple thresholding algorithms are often insufficiently robust due either to noise or inconsistent data. This paper proposes a simple 1D convolutional neural net (CNN) architecture as a generalized solution for typical time segmentation tasks. The layer architecture, training methods, and methods for simple customization will be described as well as the results of application to three separate data streams: facility condition segmentation, video highlight segmentation, and calorimeter time-series segmentation. In all three test cases the 1D-CNN performs better than tailored integral/derivative/thresholding algorithms across a range of signal-to-noise levels.

CNN↗

1D-Convolutional Neural Network Architecture for Generalized Time-series Segmentation

Time segmentation of experimental data is a common and often difficult task. Consequently, it is of interest to automate this type of segmentation to reduce manual inputs, which are labor intensive and less consistent. However, simple thresholding algorithms are often insufficiently robust due either to noise or inconsistent data. This paper proposes a simple 1D convolutional neural net (CNN) architecture as a generalized solution for typical time segmentation tasks. The layer architecture, training methods, and methods for simple customization will be described as well as the results of application to three separate data streams: facility condition segmentation, video highlight segmentation, and calorimeter time-series segmentation. In all three test cases the 1D-CNN performs better than tailored integral/derivative/thresholding algorithms across a range of signal-to-noise levels.

CNN↗

Array processor architecture connection network

A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection network includes a plurality of switching elements interposed between the processor array and the memory modules array in an Omega networking architecture. Each switching element includes a first and a second processor side port, a first and a second memory module side port, and control logic circuitry for providing data connections between the first and second processor ports and the first and second memory module ports. The control logic circuitry includes strobe logic for examining data arriving at the first and the second processor ports to indicate when the data arriving is requesting data from a requesting processor to a requested memory module. Further, connection circuitry is associated with the strobe logic for examining requesting data arriving at the first and the second processor ports for providing a data connection therefrom to the first and the second memory module ports in response thereto when the data connection so provided does not conflict with a pre-established data connection currently in use.

Barnes, George H.↗

Planning assistance for the NASA 30/20 GHz program. Network control architecture study.

Network Control Architecture for a 30/20 GHz flight experiment system operating in the Time Division Multiple Access (TDMA) was studied. Architecture development, identification of processing functions, and performance requirements for the Master Control Station (MCS), diversity trunking stations, and Customer Premises Service (CPS) stations are covered. Preliminary hardware and software processing requirements as well as budgetary cost estimates for the network control system are given. For the trunking system control, areas covered include on board SS-TDMA switch organization, frame structure, acquisition and synchronization, channel assignment, fade detection and adaptive power control, on board oscillator control, and terrestrial network timing. For the CPS control, they include on board processing and adaptive forward error correction control.

Inukai, T.↗

Space Communications Technology Conference: Onboard Processing and Switching

Papers and presentations from the conference are presented. The topics covered include the following: satellite network architecture, network control and protocols, fault tolerance and autonomy, multichanned demultiplexing and demodulation, information switching and routing, modulation and coding, and planned satellite communications systems.

Source record↗