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At least 73 records · Page 4

Vehicle safety telemetry for automated highways

The emphasis in current, automatic vehicle testing and diagnosis is primarily centered on the proper operation of the engine. Lateral and longitudinal guidance technologies, including speed control and headway sensing for collision avoidance, are reviewed. The principal guidance technique remains the buried wire. Speed control and headway sensing, even though they show the same basic elements in braking and fuel systems, are proceeding independently. The applications of on-board electronic and microprocessor techniques were investigated; each application (emission control, spark advance, or anti-slip braking) is being treated as an independent problem is proposed. A unified bus system of distributed processors for accomplishing the various functions and testing required for vehicles equipped to use automated highways.

Hansen, G. R.↗

Computational requirements for on-orbit identification of space systems

For the future space systems, on-orbit identification (ID) capability will be required to complement on-orbit control, due to the fact that the dynamics of large space structures, spacecrafts, and antennas will not be known sufficiently from ground modeling and testing. The computational requirements for ID of flexible structures such as the space station (SS) or the large deployable reflectors (LDR) are however, extensive due to the large number of modes, sensors, and actuators. For these systems the ID algorithm operations need not be computed in real-time, only in near real-time, or an appropriate mission time. Consequently the space systems will need advanced processors and efficient parallel processing algorithm design and architectures to implement the identification algorithms in near real-time. The MAX computer currently being developed may handle such computational requirements. The purpose is to specify the on-board computational requirements for dynamic and static identification for large space structures. The computational requirements for six ID algorithms are presented in the context of three examples: the JPL/AFAL ground antenna facility, the space station (SS), and the large deployable reflector (LDR).

Hadaegh, Fred Y.↗

On-board processing for telecommunications satellites

In this decade, communications satellite systems will probably face dramatic challenges from alternative transmission means. To balance and overcome such competition, and to prepare for new requirements, INTELSAT has developed several on-board processing techniques, including Satellite-Switched TDMA (SS-TDMA), Satellite-Switched FDMA (SS-FDMA), several Modulators/Demodulators (Modem), a Multicarrier Multiplexer and Demodulator MCDD), an International Business Service (IBS)/Intermediate Data Rate (IDR) BaseBand Processor (BBP), etc. Some proof-of-concept hardware and software were developed, and tested recently in the INTELSAT Technical Laboratories. These techniques and some test results are discussed.

Nuspl, P. P.↗

30 GHz Commercial Satellite Receivers

NASA's research and development work in satellite communications for the past 10 years has included a major technology thrust aimed at opening the Ka frequency band to commercial exploitation. This has included the development and testing of advanced system network architectures, on-board switching and processing, multibeam and phased array antennas, and satellite and ground terminal RF and digital hardware. Development work in system hardware has focused on critical components including power amplifiers, satellite IF switch matrices, low noise receivers, baseband processors, and high data rate bandwidth efficient modems. This paper describes NASA's work in developing and testing 30 GHz low noise satellite receivers for commercial space communications uplink applications. Frequencies allotted for fixed service commercial satellite communications in the Ka band are 27.5 - 30.0 GHz for uplink transmission and 17.7 - 20.2 GHz for downlink transmission. The relatively large 2.5 GHz bandwidth lends itself to wideband, high data rate digital transmission applications.

Kerczewski, Robert J.↗

On-board processing concepts for future satellite communications systems

The initial definition of on-board processing for an advanced satellite communications system to service domestic markets in the 1990's is discussed. An exemplar system with both RF on-board switching and demodulation/remodulation baseband processing is used to identify important issues related to system implementation, cost, and technology development. Analyses of spectrum-efficient modulation, coding, and system control techniques are summarized. Implementations for an RF switch and baseband processor are described. Among the major conclusions listed is the need for high gain satellites capable of handling tens of simultaneous beams for the efficient reuse of the 2.5 GHz 30/20 frequency band. Several scanning beams are recommended in addition to the fixed beams. Low power solid state 20 GHz GaAs FET power amplifiers in the 5W range and a general purpose digital baseband processor with gigahertz logic speeds and megabits of memory are also recommended.

Brandon, W. T.↗

Automatic Fault Protection in the Voyager Spacecraft

Due to reliability requirements placed on the Voyager spacecraft system design and a mission resulting in long two-way, light time communication links, on-board automatic fault detection and correction capabilities are a significant feature of that spacecraft's design. Most of the protection to otherwise mission-catastrophic failures is implemented in the software of the voyager's central computer, while some resides in an attitude control-dedicated processor. This paper will present the role that automatic fault protection plans in achieving Voyager's overall reliability, its design evolution, and how its design was validated during system testing. In-flight experience will also be described, and from the lessons learned there-in, conclusions and recommendations will be drawn for the benefit of future designs.

Jones, C. P.↗

Application of microprocessors to spacecraft synthetic aperture radar processing

A ground-based digital synthetic aperture radar (SAR) processor capable of correlating images from raw spacecraft data at real-time rates is currently under development. The processor design requirements are particularly formidable due to (1) range migration effects resulting from planetary curvature and rotation, (2) antenna beam pointing errors, and (3) variation of the Doppler reference function with changing orbital parameters. Based upon the current effort, this paper describes a candidate real-time on-board SAR processing implementation approach that might evolve for future spacecraft applications. Key features include the use of custom large scale integration (LSI) charge-coupled device (CCD) technology to accomplish the correlation functions and microprocessor technology to effect control.

Arens, W. E.↗

On-board processing satellite network architecture and control study

The market for telecommunications services needs to be segmented into user classes having similar transmission requirements and hence similar network architectures. Use of the following transmission architecture was considered: satellite switched TDMA; TDMA up, TDM down; scanning (hopping) beam TDMA; FDMA up, TDM down; satellite switched MF/TDMA; and switching Hub earth stations with double hop transmission. A candidate network architecture will be selected that: comprises multiple access subnetworks optimized for each user; interconnects the subnetworks by means of a baseband processor; and optimizes the marriage of interconnection and access techniques. An overall network control architecture will be provided that will serve the needs of the baseband and satellite switched RF interconnected subnetworks. The results of the studies shall be used to identify elements of network architecture and control that require the greatest degree of technology development to realize an operational system. This will be specified in terms of: requirements of the enabling technology; difference from the current available technology; and estimate of the development requirements needed to achieve an operational system. The results obtained for each of these tasks are presented.

Campanella, S. Joseph↗

The SIR-C ground data system: Digital processor, data products, information flow

The SIR-C (Shuttle Imaging Radar) instrument will collect both C-Band and L-Band data with each frequency band consisting of direct (HH or VV) and cross-polarized (HV or VH) data. Considering all possible combinations as many as eight different data channels will be available for any given target area. This data will be digitized and formatted on-board for direct downlink via the Tracking and Data Relay Satellite System (TDRSS), or it will be buffered through on-board high density digital recorders for storage or transmission when TDRSS is available. The data is received by the TDRSS ground station at White Sands and is nominally relayed via DOMSAT to the high data rate recording facility at GSFC. The tapes are then shipped to JPL for processing into imagery and eventual distribution to the SIR-C investigators.

Curlander, John C.↗

Landsat 2 on-board computer

The Landsat Spacecraft Project (formerly known as ERTS) was based essentially on the use of Nimbus spacecraft hardware. It was soon recognized that the availability of only 30 stored command locations (which were sufficient for the Nimbus mission) would limit the operation of the Landsat 1 mission with much higher power sensors, recorders, and wideband communications being cycled on and off throughout the orbit. The solution described is a simple memory with hard wired logic, of a design that can interface with the existing hardware, without modifications. The design was implemented using an existing APO (Advanced Onboard Processor) and a 4096 word X 18 bit plated wire memory. (The AOP has been subsequently designated the NASA Standard Spacecraft Computer.)

Lesko, J. G., Jr.↗

Multiple-access phased array antenna simulator for a digital beam forming system investigation

Future versions of data relay satellite systems are currently being planned by NASA. Being given consideration for implementation are on-board digital beamforming techniques which will allow multiple users to simultaneously access a single S-band phased array antenna system. To investigate the potential performance of such a system, a laboratory simulator has been developed at NASA's Lewis Research Center. This paper describes the system simulator, and in particular, the requirements, design, and performance of a key subsystem, the phased array antenna simulator, which provides realistic inputs to the digital processor including multiple signals, noise, and nonlinearities.

Kerczewski, Robert J.↗

Multiple-access phased array antenna simulator for a digital beam-forming system investigation

Future versions of data relay satellite systems are currently being planned by NASA. Being given consideration for implementation are on-board digital beamforming techniques which will allow multiple users to simultaneously access a single S-band phased array antenna system. To investigate the potential performance of such a system, a laboratory simulator has been developed at NASA's Lewis Research Center. This paper describes the system simulator, and in particular, the requirements, design and performance of a key subsystem, the phased array antenna simulator, which provides realistic inputs to the digital processor including multiple signals, noise, and nonlinearities.

Kerczewski, Robert J.↗

COMSAT Laboratories' on-board baseband switch development

Work performed at COMSAT Laboratories to develop a prototype on-board baseband switch is summarized. The switch design is modular to accommodate different service types, and the architecture features a high-speed optical ring operating at 1 Gbit/s to route input (up-link) channels to output (down-link) channels. The switch is inherently a packet switch, but can process either circuit-switched or packet-switched traffic. If the traffic arrives at the satellite in a circuit-switched mode, the input processor packetizes it and passes it on to the switch. The main advantage of the packet approach lies in its simplified control structure. Details of the switch architecture and design, and the status of its implementation, are presented.

Pontano, B. A.↗

CCD architecture for spacecraft SAR image processing

A real-time synthetic aperture radar (SAR) image processing architecture amenable to future on-board spacecraft applications is currently under development. Using state-of-the-art charge-coupled device (CCD) technology, low cost and power are inherent features. Other characteristics include the ability to reprogram correlation reference functions, correct for range migration, and compensate for antenna beam pointing errors on the spacecraft in real time. The first spaceborne demonstration is scheduled to be flown as an experiment on a 1982 Shuttle imaging radar mission (SIR-B). This paper describes the architecture and implementation characteristics of this initial spaceborne CCD SAR image processor.

Arens, W. E.↗

Development and demonstration of an on-board mission planner for helicopters

Mission management tasks can be distributed within a planning hierarchy, where each level of the hierarchy addresses a scope of action, and associated time scale or planning horizon, and requirements for plan generation response time. The current work is focused on the far-field planning subproblem, with a scope and planning horizon encompassing the entire mission and with a response time required to be about two minutes. The far-feld planning problem is posed as a constrained optimization problem and algorithms and structural organizations are proposed for the solution. Algorithms are implemented in a developmental environment, and performance is assessed with respect to optimality and feasibility for the intended application and in comparison with alternative algorithms. This is done for the three major components of far-field planning: goal planning, waypoint path planning, and timeline management. It appears feasible to meet performance requirements on a 10 Mips flyable processor (dedicated to far-field planning) using a heuristically-guided simulated annealing technique for the goal planner, a modified A* search for the waypoint path planner, and a speed scheduling technique developed for this project.

Deutsch, Owen L.↗

Planning assistance for the 30/20 GHz program, volume 2

In the baseline concept development the communications payload on Flight 1 was specified to consist of on-board trunking and emergency communications systems (ECS). On Flight 2 the communications payloads consisted of trunking and CPS on-board systems, the CPS capability replacing the Flight 1 ECS. No restriction was placed on the launch vehicle size. Constraints placed on multiple concept development effort were that launch vehicle size for Concept 1 was restricted to SUSS-D and for Concept 2 a SUSS-A. The design concept development was based on satisfying the baseline requirements set forth in the SOW for a single demonstration flight system. Key constraints on contractors were cost and launch vehicle size. Five major areas of new technology development were reviewed: (1) 30 GHz low noise receivers; (2) 20 GHz Power Amplifiers; (3) SS-TDMA switch; (4) Baseband Processor; (5) Multibeam Antennas.

Al-Kinani, G.↗

Autonomous exploration system: Techniques for interpretation of multispectral data

An on-board autonomous exploration system that fuses data from multiple sensors, and makes decisions based on scientific goals is being developed using a series of artificial neural networks. Emphasis is placed on classifying minerals into broad geological categories by analyzing multispectral data from an imaging spectrometer. Artificial neural network architectures are being investigated for pattern matching and feature detection, information extraction, and decision making. As a first step, a stereogrammetry net extracts distance data from two gray scale stereo images. For each distance plane, the output is the probable mineral composition of the region, and a list of spectral features such as peaks, valleys, or plateaus, showing the characteristics of energy absorption and reflection. The classifier net is constructed using a grandmother cell architecture: an input layer of spectral data, an intermediate processor, and an output value. The feature detector is a three-layer feed-forward network that was developed to map input spectra to four geological classes, and will later be expanded to encompass more classes. Results from the classifier and feature detector nets will help to determine the relative importance of the region being examined with regard to current scientific goals of the system. This information is fed into a decision making neural net along with data from other sensors to decide on a plan of activity. A plan may be to examine the region at higher resolution, move closer, employ other sensors, or record an image and transmit it back to Earth.

Yates, Gigi↗

On-board fault management for autonomous spacecraft

The dynamic nature of the Cargo Transfer Vehicle's (CTV) mission and the high level of autonomy required mandate a complete fault management system capable of operating under uncertain conditions. Such a fault management system must take into account the current mission phase and the environment (including the target vehicle), as well as the CTV's state of health. This level of capability is beyond the scope of current on-board fault management systems. This presentation will discuss work in progress at TRW to apply artificial intelligence to the problem of on-board fault management. The goal of this work is to develop fault management systems. This presentation will discuss work in progress at TRW to apply artificial intelligence to the problem of on-board fault management. The goal of this work is to develop fault management systems that can meet the needs of spacecraft that have long-range autonomy requirements. We have implemented a model-based approach to fault detection and isolation that does not require explicit characterization of failures prior to launch. It is thus able to detect failures that were not considered in the failure and effects analysis. We have applied this technique to several different subsystems and tested our approach against both simulations and an electrical power system hardware testbed. We present findings from simulation and hardware tests which demonstrate the ability of our model-based system to detect and isolate failures, and describe our work in porting the Ada version of this system to a flight-qualified processor. We also discuss current research aimed at expanding our system to monitor the entire spacecraft.

Fesq, Lorraine M.↗