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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4

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NASA NTRS1988

Ku-band high efficiency GaAs MMIC power amplifiers

The development of Ku-band high efficiency GaAs MMIC power amplifiers is examined. Three amplifier modules operating over the 13 to 15 GHz frequency range are to be developed. The first MMIC is a 1 W variable power amplifier (VPA) with 35 percent efficiency. On-chip digital gain control is to be provided. The second MMIC is a medium power amplifier (MPA) with an output power goal of 1 W and 40 percent power-added efficiency. The third MMIC is a high power amplifier (HPA) with 4 W output power goal and 40 percent power-added efficiency. An output power of 0.36 W/mm with 49 percent efficiency was obtained on an ion implanted single gate MESFET at 15 GHz. On a dual gate MESFET, an output power of 0.42 W/mm with 27 percent efficiency was obtained. A mask set was designed that includes single stage, two stage, and three stage single gate amplifiers. A single stage 600 micron amplifier produced 0.4 W/mm output power with 40 percent efficiency at 14 GHz. A four stage dual gate amplifier generated 500 mW of output power with 20 dB gain at 17 GHz. A four-bit digital-to-analog converter was designed and fabricated which has an output swing of -3 V to +/- 1 V.

Tserng, H. Q.↗

NASA NTRS1995

Wideband fixed-tuned SIS receiver for 200-GHz operation

We report on the design and development of a heterodyne receiver, designed to cover the frequency range 176-256 GHz. This receiver incorporates a niobium superconductor-insulator-superconductor (SIS) tunnel junction mixer, which, chiefly for reasons of reliability and ease of operation, is a fixed-tuned waveguide design. On-chip tuning is provided to resonate out the junction's geometric capacitance and produce a good match to the waveguide circuit. Laboratory measurements on the first test receiver indicate that the required input bandwidth (about 40%) is achieved with an average receiver noise temperature of below 50 K. Mixer conversion gain is observed at some frequencies, and the lowest measured receiver noise is less than 30 K. Furthermore, the SIS mixer used in this receiver is of simple construction, is easy to assemble and is therefore a good candidate for duplication.

RECEIVER NOISE TEMPERATURE↗

NASA NTRS1995

Built-In Diagnostics (BID) Of Equipment/Systems

Diagnostician(TM)-on-Chip (DOC) technology identifies faults and commands systems reconfiguration. Smart microcontrollers operating in conjunction with other system-control circuits, command self-correcting system/equipment actions in real time. DOC microcontroller generates commands for associated built-in test equipment to stimulate unit of equipment diagnosed, collects and processes response data obtained by built-in test equipment, and performs diagnostic reasoning on response data, using diagnostic knowledge base derived from design data.

Granieri, Michael N.↗

NASA NTRS1994

Waveguide-coupled resonator filters on AlN on silicon

In the effort to continually reduce the size and cost of wireless communications products the level of integration has improved dramatically in recent years. In order to reduce future generations of wireless systems to single chip form, there is a need for on-chip filtering capabilities. In this paper, the first report of an experimental waveguide-coupled resonator filter for cellular radio applications is presented. Measured results indicate a typical insertion loss of 26 dB at a center frequency of 132 MHz using a 2 um AlN film on (001) less than 110 greater than Si. In addition, a laser probe analysis has been conducted and a theoretical analysis of the first order reflection coefficients is presented.

Liaw, H. M.↗

NASA NTRS1995

MEMS in Space Systems

Micro-electro-mechanical systems (MEMS) provide an emerging technology that has the potential for revolutionizing the way space systems are designed, assembled, and tested. The high launch costs of current space systems are a major determining factor in the amount of functionality that can be integrated in a typical space system. MEMS devices have the ability to increase the functionality of selected satellite subsystems while simultaneously decreasing spacecraft weight. The Air Force Phillips Laboratory (PL) is supporting the development of a variety of MEMS related technologies as one of several methods to reduce the weight of space systems and increase their performance. MEMS research is a natural extension of PL research objectives in micro-electronics and advanced packaging. Examples of applications that are under research include on-chip micro-coolers, micro-gyroscopes, vibration sensors, and three-dimensional packaging technologies to integrate electronics with MEMS devices. The first on-orbit space flight demonstration of these and other technologies is scheduled for next year.

Lyke, J. C.↗

NASA NTRS1996

The Single Event Effect Characteristics of the 486-DX4 Microprocessor

This research describes the development of an experimental radiation testing environment to investigate the single event effect (SEE) susceptibility of the 486-DX4 microprocessor. SEE effects are caused by radiation particles that disrupt the logic state of an operating semiconductor, and include single event upsets (SEU) and single event latchup (SEL). The relevance of this work can be applied directly to digital devices that are used in spaceflight computer systems. The 486-DX4 is a powerful commercial microprocessor that is currently under consideration for use in several spaceflight systems. As part of its selection process, it must be rigorously tested to determine its overall reliability in the space environment, including its radiation susceptibility. The goal of this research is to experimentally test and characterize the single event effects of the 486-DX4 microprocessor using a cyclotron facility as the fault-injection source. The test philosophy is to focus on the "operational susceptibility," by executing real software and monitoring for errors while the device is under irradiation. This research encompasses both experimental and analytical techniques, and yields a characterization of the 486-DX4's behavior for different operating modes. Additionally, the test methodology can accommodate a wide range of digital devices, such as microprocessors, microcontrollers, ASICS, and memory modules, for future testing. The goals were achieved by testing with three heavy-ion species to provide different linear energy transfer rates, and a total of six microprocessor parts were tested from two different vendors. A consistent set of error modes were identified that indicate the manner in which the errors were detected in the processor. The upset cross-section curves were calculated for each error mode, and the SEU threshold and saturation levels were identified for each processor. Results show a distinct difference in the upset rate for different configurations of the on-chip cache, as well as proving that one vendor is superior to the other in terms of latchup susceptibility. Results from this testing were also used to provide a mean-time-between-failure estimate of the 486-DX4 operating in the radiation environment for the International Space Station.

Kouba, Coy↗

NASA NTRS1995

A Compact Polarization Imager

A new type of image detector has been designed to analyze the polarization of light simultaneously at all picture elements (pixels) in a scene. The Integrated Dual Imaging Detector (IDID) consists of a polarizing beamsplitter bonded to a custom-designed charge-coupled device with signal-analysis circuitry, all integrated on a silicon chip. The IDID should simplify the design and operation of imaging polarimeters and spectroscopic imagers used, for example, in atmospheric and solar research. Other applications include environmental monitoring and robot vision. Innovations in the IDID include two interleaved 512 x 1024 pixel imaging arrays (one for each polarization plane), large dynamic range (well depth of 10(exp 6) electrons per pixel), simultaneous readout and display of both images at 10(exp 6) pixels per second, and on-chip analog signal processing to produce polarization maps in real time. When used with a lithium niobate Fabry-Perot etalon or other color filter that can encode spectral information as polarization, the IDID can reveal tiny differences between simultaneous images at two wavelengths.

Thompson, Karl E.↗

NASA NTRS1995

High Speed CMOS Binary Active Pixel Image Sensor

A highly integrated active pixel sensor with on-chip 1 bit thresholding circuitry achieving an 8,000.

CMOS Image Sensor↗

NASA NTRS1995

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

Space Microelectronics Image Sensors APS Digital I↗

NASA NTRS1995

CMOS Image Sensors: Electronic Camera On A Chip

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Space Microelectronics Image Sensors APS Digital I↗

NASA NTRS1995

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

Space Microelectronics Image Sensors APS Digital I↗

NASA NTRS1994

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

JPL, under sponsorship from the NASA Office of Advanced Concepts and Technology, has been developing a second-generation solid-state image sensor technology. Charge-coupled devices (CCD) are a well-established first generation image sensor technology. For both commercial and NASA applications, CCDs have numerous shortcomings. In response, the active pixel sensor (APS) technology has been under research. The major advantages of APS technology are the ability to integrate on-chip timing, control, signal-processing and analog-to-digital converter functions, reduced sensitivity to radiation effects, low power operation, and random access readout.

solid-state image sensors active pixel sensor APS ↗

NASA NTRS1993

Active Pixel Sensors: Are CCD's Dinosaurs?

Charge-coupled devices (CCD's) are presently the technology of choice for most imaging applications. In the 23 years since their invention in 1970, they have evolved to a sophisticated level of performance. However, as with all technologies, we can be certain that they will be supplanted someday. In this paper, the Active Pixel Sensor (APS) technology is explored as a possible successor to the CCD. An active pixel is defined as a detector array technology that has at least one active transistor within the pixel unit cell. The APS eliminates the need for nearly perfect charge transfer -- the Achilles' heel of CCDs. This perfect charge transfer makes CCD's radiation 'soft,' difficult to use under low light conditions, difficult to manufacture in large array sizes, difficult to integrate with on-chip electronics, difficult to use at low temperatures, difficult to use at high frame rates, and difficult to manufacture in non-silicon materials that extend wavelength response.

Fossum, Eric R.↗

NASA NTRS1993

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Mendis, Sunetra K.↗

NASA NTRS1992

Fault detection and bypass in a sequence information signal processor

The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.

Peterson, John C.↗

NASA NTRS1977

Bubble domain circuit organization

An on-chip bubble domain circuit organization. One or more storage registers are connected to a propagation path whereby data in the form of magnetic bubble domains (bubbles) may be transferred into and out of the storage registers. The propagation path includes a generator for producing the initial bubbles which are expanded into any desired number of new bubbles by a unique multiple output replicator. A unique input decoder is utilized to determine to which storage register the bubbles from the replicator will be directed along the propagation path. Those bubbles not selected may be annihilated. An output decoder utilizing essentially the same decoding scheme as the input decoder, selectively receives bubbles from the storage register. A transfer and replicate switch is utilized between the storage register and output decoder to selectively transfer bubbles to the output decoder. The output decoder may collapse all of the bubbles from certain storage registers so that only the information from the selected storage register reaches the detector. The detectors in turn produce the chip output signal. External control electronics are utilized to control the selective operation of the various devices utilized in the propagation path.

Chen, Thomas T.↗

NASA NTRS1995

Application of New Technology to Future Celestial Trackers

New developments in image sensors and optical materials have opened the door to dramatic mass and power reductions in celestial tracker designs. The rapid development of active pixel sensors (APS) has provided a new detector choice offering high on-chip integration of support circuitry at reduced power consumption. Silicon-Carbide (Si-C) optics are one of the new developments in low-mass optical components. We describe the celestial tracker needs of an Autonomous Feature and Star Tracking (AFAST) system designed for autonomous spacecraft control. Details of a low mass celestial tracker, based on a low power APS array and optimized for an AFAST system, are discussed.

active↗

NASA NTRS1996

Programmable Multiresolution CMOS Active Pixel Sensor

CMOS active pixel sensors (APS) allow the flexibility of placing signal processing circuitry on the imaging focal plane. The multiresolution CMOS APS can perform block averaging on-chip to eliminate the off-chip software intensive image processing. This 128 x 128 APS array can be read out at any user-defined resolution by configuring a set of digital shift registers. The resolution frame rate is 30 Hz with higher rates for all other image resolutions.

APS↗