Methods for dc to ac conversion Semiannual status report
Thin film deposition on metal oxide semiconductor devices, and dc to ac conversion methods
ALTERNATING CURRENT /AC/↗
SEARCH · Search NASA
Results for “oxide semiconductor”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
CMOS Active Pixel Sensors for Low Power, Highly Miniaturized Imaging Systems
The complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology has been developed over the past three years by NASA at the Jet Propulsion Laboratory, and has reached a level of performance comparable to CCDs with greatly increased functionality but at a very reduced power level.
CMOS complementary metal-oxide-semiconductor activ↗
NASA Engineering and Safety Center Technical Bulletin No. 10-01: Power MOSFET Thermal Instability
In the quest for faster switching times and lower “on resistance” the Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET), produced since 1998, has achieved most intended goals. Unfortunately, lower “on resistance” and higher switching speeds in the designs now being produced allow the charge carrier dominated region to develop conditions that could lead to thermal runaway. Temperatures above 450º C on any location within the part can cause the metals to begin migrating causing a fatal short circuit.
Metal-Oxide Semiconductor Field-Effect Transistor ↗
Thermally grown oxide and diffusions for automatic processing of integrated circuits
A totally automated facility for semiconductor oxidation and diffusion was developed using a state-of-the-art diffusion furnace and high temperature grown oxides. Major innovations include: (1) a process controller specifically for semiconductor processing; (2) an automatic loading system to accept wafers from an air track, insert them into a quartz carrier and then place the carrier on a paddle for insertion into the furnace; (3) automatic unloading of the wafers back onto the air track, and (4) boron diffusion using diborane with plus or minus 5 percent uniformity. Processes demonstrated include Wet and dry oxidation for general use and for gate oxide, boron diffusion, phosphorous diffusion, and sintering.
Kennedy, B. W.↗
Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron
Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.
Danchenko, V.↗
Re-Verification of the IRHN57133SE and IRHN57250SE for Single Event Gate Rupture and Single Event Burnout
The vertical metal oxide semiconductor field-effect transistor (MOSFET) is a widely used power transistor onboard a spacecraft. The MOSFET is typically employed in power supplies and high current switching applications. Due to the inherent high electric fields in the device, power MOSFETs are sensitive to heavy ion irradiation and can fail catastrophically as a result of single event gate rupture (SEGR) or single event burnout (SEB). Manufacturers have designed radiation-hardened power MOSFETs for space applications. These radiation hardened devices are not immune to SEGR or SEB but, rather, can exhibit them at a much more damaging ion than their non-radiation hardened counterparts. See [1] through [5] for more information.This effort was to investigate the SEGR and SEB responses of two power MOSFETs from IR(the IRHN57133SE and the IRHN57250SE) that have recently been produced on a new fabrication line. These tests will serve as a limited verification of these parts, but it is acknowledged that further testing on the respective parts may be needed for some mission profiles.
Single Event Gate Rupture (SEGR)↗
IR DirectFET Extreme Environments Evaluation Final Report
In 2007, International Rectifier (IR) introduced a new version of its DirectFET metal oxide semiconductor field effect transistor (MOSFET) packaging. The new version (referred to as 'Version 2') enhances device moisture resistance, makes surface mount (SMT) assembly of these devices to printed wiring boards (PWBs) more repeatable, and subsequent assembly inspection simpler. In the present study, the National Aeronautics Space Administration (NASA) Jet Propulsion Laboratory (JPL), in collaboration with Stellar Microelectronics (Stellar), continued an evaluation of the DirectFET that they started together in 2006. The present study focused on comparing the two versions of the DirectFET and examining the suitability of the DirectFET devices for space applications. This study evaluated both versions of two DirectFET packaged devices that had both been shown in the 2006 study to have the best electrical and thermal properties: the IRF6635 and IRF6644. The present study evaluated (1) the relative electrical and thermal performance of both versions of each device, (2) the performance through high reliability testing, and (3) the performance of these devices in combination with a range of alternate solder alloys in the extreme thermal environments of deep space....
electronic parts packaging↗
Reliability studies in semiconductor fabrication
Profiling procedures including computer program (OLS) for measuring junction depth in anodic oxidation - semiconductor fabrication reliability studies
Source record↗
Low cost AMOS solar cell development
Recent developments at JPL have demonstrated that high conversion efficiencies are found with GaAs metal semiconductor solar cells when a particular heat treatment processing step is used to introduce an interfacial layer between the metal and the semiconductor. The new cell, called AMOS (Antireflection-Coated Metal-Oxide-Semiconductor), has open circuit voltages of 0.68-0.72 volts and efficiencies of 15% under terrestrial sunlight, as compared to values of 0.45-0.48 volts and 10%, respectively, for similar cells without an interfacial layer. Potentially higher efficiencies are feasible as further improvements are made in optimizing the interfacial layer effect and in increasing the blue response of the cells. A thin film AMOS cell is proposed that uses a thin recrystallized germanium (Ge) layer between a low cost metal substrate and the vapor phase epitaxially (VPE)-grown GaAs.
Stirn, R. J.↗
Single crystal and polycrystalline GaAs solar cells using AMOS technology
A description is given of current technology for fabricating single AMOS (antireflection-coated metal oxide semiconductor) solar cells, with attention given to thermal, plasma, and anodic oxidation, native oxide stripping, and X-ray photoelectron spectroscopy results. Some preliminary results are presented on the chemistry and electrical characterization of such cells, and the characteristics of cells fabricated on sliced polycrystalline GaAs wafers are examined. Consideration is also given to the recrystallization of evaporated Ge films for use as low-cost substrates for polycrystalline GaAs solar cells.
Stirn, R. J.↗
Investigation of Field Emitter Array Vacuum Microtriodes for Space Electronics Applications
Research into processing techniques for fabrication of vacuum microelectronic devices has been carried out, with special emphasis being given to the growth of silicon dioxide thin films. Oxide films ranging from 30 nm to approximately 2 micrometers have been grown on single crystal silicon wafers. Metal-oxide-semiconductor capacitor test structures have been made from some of these oxide films, and current-versus-voltage plots for these structures have been measured. It has been observed that the rate of applied voltage across the oxide films produces marked differences in measured leakage current. Breakdown fields across two of the thinnest oxide films have been measured and are comparable with highest values reported in literature. Several silicon wafers were processed to make field- emitter array diodes, and were delivered to collaborators at NASA-Lewis Research Center for final fabrication steps and testing.
Smith, Mark A.↗
Electrical characterization of plasma-grown oxides on gallium arsenide
Plasma-grown GaAs oxides and their interfaces have been characterized by measuring the electrical properties of metal-oxide-semiconductor capacitors and of Schottky junctions. The current transport mechanism in the oxide at high electrical field was found to be Frankel-Poole emission, with an electron trap center at 0.47 eV below the conduction band of the oxide. The interface-state density, evaluated from capacitance and conductance measurements, exhibits a U-shaped interface-state continuum extending over the entire band gap. Two discrete deep states with high concentration are superimposed on this continuum at 0.40 and 0.70 eV below the conduction band. The results obtained from measurements on Schottky junctions have excluded the possibility that these two deep states originate from plasma damage. Possible origins of these states are discussed in this paper.
Hshieh, F. I.↗
Fabrication of OSOS cells by neutral ion beam sputtering
Oxide semiconductor on silicon (OSOS) solar cells have been fabricated from various indium tin oxide (In2O3)x(SnO2)1-x compositions sputtered onto p-type single crystal silicon substrates with a neutralized argon ion beam. High temperature processing or annealing was not required. The highest efficiency was achieved with x = 0.91 and was 12 percent. The cells are environmentally rugged, chemically stable, and show promise for still higher efficiencies. Moreover, the ion beam sputtering fabrication technique is amenable to low cost, continuous processing.
Burk, D. E.↗
The interrelation of process techniques and space radiation effects in metal-insulator-semiconductor structures Final report, 21 Apr. 1966 - 31 Jul. 1967
Interrelation of process techniques and space radiation effects in metal oxide semiconductors
Dennehy, W. J.↗
Effect of environment on thermal control coatings
Thermal control coatings, cathodic processes on semiconductor zinc oxide, and semiconductor electrolyte interface capacitance
TEMPERATURE CONTROL↗
Behavior of inversion layers in 3C silicon carbide
A study on the field-induced surface-charge region in 3C silicon carbide (SiC) using 1 MHz capacitance-voltage (C-V) measurements at room temperature is here reported. A double column mercury probe was used on oxidized SiC substrates to form metal-oxide-semiconductor (MOS) structures. These structures were characterized in terms of the substrate doping profile, effective fixed oxide charge, and interface trap density. A distinctive feature of the MOS C-V curves from accumulation to inversion is that after going into deep depletion the capacitance rises to its equilibrium inversion level during the voltage sweep. Capacitance transient measurements indicate that the minority-carrier generation occurs at the SiO2/SiC interface.
Avila, R. E.↗
Multi-Dimensional Quantum Tunneling and Transport Using the Density-Gradient Model
We show that quantum effects are likely to significantly degrade the performance of MOSFETs (metal oxide semiconductor field effect transistor) as these devices are scaled below 100 nm channel length and 2 nm oxide thickness over the next decade. A general and computationally efficient electronic device model including quantum effects would allow us to monitor and mitigate these effects. Full quantum models are too expensive in multi-dimensions. Using a general but efficient PDE solver called PROPHET, we implemented the density-gradient (DG) quantum correction to the industry-dominant classical drift-diffusion (DD) model. The DG model efficiently includes quantum carrier profile smoothing and tunneling in multi-dimensions and for any electronic device structure. We show that the DG model reduces DD model error from as much as 50% down to a few percent in comparison to thin oxide MOS capacitance measurements. We also show the first DG simulations of gate oxide tunneling and transverse current flow in ultra-scaled MOSFETs. The advantages of rapid model implementation using the PDE solver approach will be demonstrated, as well as the applicability of the DG model to any electronic device structure.
Biegel, Bryan A.↗
Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches
Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN bipolar junction transistors (BJTs), metal-oxide-semiconductor field effect transistors (MOSFETs), and static induction transistors (SITs) are given. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Postirradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.
Schwarze, G. E.↗