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Reproducible magnetic field sweep.
Reproducible magnetic field sweep consisting of phase-locked system with digital frequency synthesizer
A proposed spacecraft-to-earth communications link - the unified carrier approach.
Unified carrier, range tracking and communications system using phase-locked loop techniques for coherent spacecraft-to-Earth communications
Interior servicing platform simplifies maintenance of storage tanks
Rapid synchronization of phase-locked oscillators is best achieved by the swept-frequency acquisition technique, wherein the Voltage-Controlled Oscillator /VCO/ is linearly swept through the uncertainty band. The theoretically predicted sweep rates of this technique and the observed experimental results differ by less than seven percent.
Single-sideband modulator accurately reproduces phase information in 2-Mc signals
Phase-locked oscillator system employing solid state components acts as a single-sideband modulator to accurately reproduce phase information in 2-Mc signals. This system is useful in telemetry, aircraft communications and position-finding stations, and VHF test circuitry.
Use of phase-locked-loop control for driving ultrasonic transducers
Phase-locked loop used as frequency control system for ultrasonic transducer
Vehicle tracking receiver design
Phase-locked loops and signal processing techniques employed in vehicle tracking receiver
Special AROD System Studies, Volume I Fifth Quarterly Report, Period Ending Dec. 31, 1964
Wideband modulation techniques and phase-locked loop studies for airborne range and orbit determination system
Stabilized gas laser oscillators Final report, 24 Jun. 1964 - 21 Jun. 1966
Phase-locking scheme for frequency-stabilized gas laser oscillators
Spacecraft telemetry and command
Probability distribution of time to first loss of lock investigated by second order phase-locked loop - spacecraft telemetry and command
Intermodulation distortion of a phase locked loop demodulator.
Intermodulation distortion of phase-locked loop demodulator as influenced by system parameters
Study of applications of retrodirective and self-adaptive electromagnetic wave phase controls to a Mars probe, part 2 Final report, 26 Jan. - 31 Dec. 1967
Phase-locked loop operation in multipath environment and multipath effect on detection for Mars probe
An all digital phase locked loop for FM demodulation.
A phase-locked loop designed with all-digital circuitry which avoids certain problems, and a digital voltage controlled oscillator algorithm are described. The system operates synchronously and performs all required digital calculations within one sampling period, thereby performing as a real-time special-purpose computer. The SNR ratio is computed for frequency offsets and sinusoidal modulation, and experimental results verify the theoretical calculations.
Synthesis and evaluation of phase detectors for active bit synchronizers
Self-synchronizing digital data communication systems usually use active or phase-locked loop (PLL) bit synchronizers. The three main elements of PLL synchronizers are the phase detector, loop filter, and the voltage controlled oscillator. Of these three elements, phase detector synthesis is the main source of difficulty, particularly when the received signals are demodulated square-wave signals. A phase detector synthesis technique is reviewed that provides a physically realizable design for bit synchronizer phase detectors. The development is based upon nonlinear recursive estimation methods. The phase detector portion of the algorithm is isolated and analyzed.
Clock synchronization of a large multiprocessor system in the presence of malicious faults
An interconnection algorithm is presented for achieving clock synchronization in a multiprocessor system. The system is assumed to be maliciously faulty, i.e., some processors are out of synchronization and lie about their clock state to other intragroup or intergroup processors. A phase-locked clock network design is proposed which groups the clocks in the system into diverse clusters. The clusters are then treated as single clock units from the perspective of the network. The algorithm minimizes the number of interconnections while permitting synchronization of large multiprocessor systems controlling time-critical applications such as aircraft, nuclear reactors and industrial processes.
Design Concept for a Rapid Automatic Sync Acquisition System
A design has been conceived for a system intended to provide rapid command sync acquisition between widely separated transmitter-receivers, such as between a spacecraft telemetry transmitter, and a ground-based receiver. Use of the system in commercial satellite communications would facilitate rapid sync acquisition between stations and regaining of data lock after interruption or equipment failure. The system is based on a rapid, automatic range-adjustment approach rather than the time-consuming cycle slipping or stepping techniques of conventional phase-locked loops.
A Long-Range Precision Ranging System
A technique is presented that may be used for precision real-time continuous range measuring at long ranges. The technique uses a carrier that is phase modulated by a pseudo-random binary sequence. The characteristics of the sequence that make it acquirable are discussed. The general form of a receiver capable of tracking the carrier is given and is shown to be a kind of phase-locked loop. A two-loop system capable of tracking a pseudo-random sequence and its clock is given. The combination of the receiver and the sequence tracking system form a ranging receiver. The power division necessary between the carrier and the sidebands is shown to be determined by the noise bandwidths of the two tracking systems. The bandwidths necessary for tracking space probes and Earth satellites are given and some experiments in radar-tracking Earth satellites are described. Based on these experiments, estimates are made of the useful range of such a system in tracking space probes.
An Arbitrary Time Interval Generator Base on Vernier Clocks with 0.67 ps Adjustable Steps Implemented in FPGA
In TDC testing and timing system implementations, it is often necessary to generate signal pulses with finely adjustable time intervals. In delay cell–based schemes, the adjustment resolution is constrained by the propagation delay of the cells—typically 15–20 ps per step—and is sensitive to temperature and supply voltage variations. This document presents a fully digital approach that uses two vernier clocks, generated by two stages of cascaded phase-locked loops (PLLs) with a slight frequency difference, to achieve adjustable timing intervals through accumulated phase differences. The scheme was validated on two families of low-cost FPGA devices, achieving adjustable step sizes of 0.67 ps and 0.97 ps.