Search NASA⌕ Search

SEARCH · Search NASA

Results for “printed circuits”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Thermal Management of Wide-Bandgap Semiconductor Amplifiers Used for Plasma Heating and Control

Princeton Fusion Systems (PFS) has designed, built, and tested a Load Switch printed circuit board (PCB) to demonstrate the capabilities of 2 kV silicon carbide (SiC) cascodes in development by Qorvo towards plasma heating and control applications. Initial tests have been conducted at low power (~100 W) for validation with thermal finite element analysis (FEA) modeling performed by the National Renewable Energy Laboratory (NREL). Comparisons of experimental data with the thermal modeling results, along with considerations for operating in plasma systems, will be discussed.

CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SU↗
DOE OSTI2025

Flexible PCB Windings Size Optimization for Winding AC Resistance Minimization Under the Sinusoidal Voltage Regime

In this paper, optimization of the winding AC resistance of the flexible printed circuit board (FPCB) wire windings is performed. A one-dimensional model of the FPCB winding is introduced and an equation for the FPCB winding AC resistance and its low and medium frequency approximation are derived. The approximate FPCB winding AC resistance equation is used to derive optimum thickness of the FPCB winding conductor thickness at which minimum of winding AC resistance (global optimum) is achieved. The Finite Element Method analysis and experimental verification of derived equations (winding resistance, impedance, power loss, and temperature measurements) is performed in order validate derived model and winding resistance equation.

42 ENGINEERING↗
DOE OSTI2025

Approaches for Water Removal in Direct-Fired sCO 2 Power Cycles

There is interest in investigation of water removal processes in direct fired sCO 2 flows, as this may potentially lead to greater system efficiency as the removal of this contaminant will result in sCO 2 behaving close to idealized behaviors. Water removal should be split into a two-step process, condensation of the water, followed by separation of the liquid phase water from the sCO 2 . The two main avenues of condensation are manipulation of pressure and temperature for phase change. For this paper, temperature-based phase change is the primary focus through the implementation of heat exchangers. Of the heat exchangers investigated it was found that printed circuit heat exchangers (PCHEs) could be an alternative for this use case, though the specific design of flow channel geometry and flow direction depends on the specific system case and cannot be determined at this point. For water separation there were four processes identified, all of which already assume water is in liquid phase at that point in the system. Of these separation avenues the best candidate is the hydrocyclone as it has a proven history of separating liquid-liquid phase mixtures with small density differences in oilfield use, in addition they have been investigated and modeled specifically for water separation for sCO 2 flows and the footprint is relatively small.

20 FOSSIL-FUELED POWER PLANTS↗
DOE OSTI2022

Flex-PCB Quench Antenna Developments at FNAL

We report flexible printed-circuit-board-based quench antenna arrays have been developed at FNAL since 2017. They proved to be low-noise, low-cost, sensitive, and non-invasive sensors for quench characterization in superconducting magnets, having the potential to extend even to quench detection. Starting with applications of small area sensors of this type, we have explored feasibility for operations at high pressure, and have invested in multi-channel quench antenna arrays covering the complete area of the innermost magnet layer of the conductor. We've also tested and optimized sensor geometry and relative orientations to increase sensitivity and spatial resolution. Beyond developments of warm and cold bore antennas, we've progressed to concepts which attach quench antennas to the conductor surfaces of accelerator magnets. Multiple programs and projects at FNAL and collaborating institutions benefited from this work already and our plans target further extensions of capabilities and applicability of these devices. In this paper we present the logic behind the development steps taken so far, status of our work and direction of near-term research on quench antennas at Fermilab.

43 PARTICLE ACCELERATORS↗
DOE OSTI2022

Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks

Malicious modifications to printed circuit boards (PCBs) are known as hardware Trojans. These may arise when malafide third parties alter PCBs premanufacturing or postmanufacturing and are a concern in safety-critical applications, such as industrial control systems. In this research, we examine how data-driven detection can be utilized to detect such Trojans at run-time. We develop a flexible and reconfigurable PCB test bed derived from the popular open-source programmable logic controller (PLC) platform “OpenPLC.” We then develop a Trojan detection framework, which utilizes and analyzes multimodal side channels (e.g., timing, magnetic signals, power, and hardware performance counters). We consider defender-configurable input/output (I/O) loopback test, comparison with design-document baselines, and magnetometer-aided monitoring of system behavior under defender-chosen excitations. Our approach can extend to golden-free environments. Golden (known-good) versions of the PCBs are assumed not available, but design information, datasheets, and component-level data are available. We demonstrate the efficacy of our approach on a range of Trojans instantiated in the test bed.

42 ENGINEERING↗
DOE OSTI2021

Design of a 2 MW ZrC/W-based molten-salt-to-sCO 2 PCHE for concentrated solar power

To increase the power cycle efficiency and lower the levelized cost of electricity (LCOE) of concentrated solar power (CSP) plants, printed circuit heat exchangers (PCHEs) capable of operating above 700 °C with molten chloride salt and a sCO 2 -based fluid are needed. In this paper, the design of a high-pressure, high-temperature, 2 MW PCHE comprised of a thermomechanically-robust, zirconium carbide/tungsten (ZrC/W) composite is conducted for CSP plants. The ZrC/W composite is a material with high thermal conductivity, high stiffness, and high failure strength at high temperatures, along with excellent resistance to thermal cycling and thermal shock. In this work, a thermomechanical design analysis was conducted to select appropriate material thicknesses of the ZrC/W plates, and to determine the geometrical dimensions and the thermal performance of the PCHE. The influences of the plate number and heat exchanger length on power density and pressure drop have also been systematically investigated. Economic analyses were conducted to compare the cost of ZrC/W-based PCHEs to those comprised of IN740H (a state-of-the-art, nickel-based superalloy) and 316 stainless steel (316SS). Finally, at a sufficiently high plate production rate, the manufacturing cost of ZrC/W-based PCHEs can be significantly lower, while achieving a much higher power density, compared with state-of-the-art, nickel alloy-based and stainless steel-based PCHEs.

14 SOLAR ENERGY↗
DOE OSTI2022

Topology optimization of an airfoil fin microchannel heat exchanger using artificial intelligence

High-performance microchannel heat exchangers are needed to supply heat for power conversion for nuclear microreactors. An airfoil fin microchannel design, constructed of Alloy 617 with helium as the working fluid, is analyzed and optimized using a design of experiments with artificial intelligence techniques. The use of airfoil fins offers the potential to reduce pressure drop across the heat exchanger, as compared to other types of channel configurations. A framework for topology optimization of airfoil fin printed circuit heat exchangers (PCHEs) has been developed that can be readily extended to different fin sizes and shapes, as well as different inlet and operating conditions, materials of construction, and working fluids. An optimization procedure is developed that employs computational fluid dynamics for a set of design points identified using Latin hypercube sampling. Computational fluid dynamics is used to analyze a simplified two-channel configuration where five design parameters are varied – inlet angle, fin scale, extent of staggering, transverse and longitudinal pitches. Two methods (a 5D polynomial and a regression neural network) are compared for generating surrogate models and the resulting response surface approximation is input to a genetic algorithm that is used to identify a set of optimal parameters. The optimal geometries are found across six channel Reynolds numbers ranging from 1000 to 5000, since inlet conditions affect flow through the heat exchanger. Additionally, a set of optimal designs that maximizes heat transfer and minimizes pressure drop is identified, and a thermal stress analysis is performed on the optimal design. Correlations for the Nusselt number and Darcy friction factor are developed that can be useful for thermal hydraulic analyses using system codes. Thermal stresses are analyzed and a brief discussion of the status of code cases of PCHEs for nuclear applications is given. Testing and thermomechanical modeling is needed to facilitate future code compliance of PCHEs for high pressure and high temperature applications.

42 ENGINEERING↗
DOE OSTI2025

All 2D Material Printed Diodes and Circuits on Paper for Sustainable Electronics

Sustainable electronics aim to reduce environmental impact by using ecofriendly materials, energy-efficient manufacturing, and recyclable components. However, existing approaches rely on complex, resource-intensive methods, rare metals, or nanomaterials with limited stability as well as plastic substrates, raising sustainability issues. Solution-processed two-dimensional (2D) materials offer a promising alternative: water-based and biocompatible conductive, semiconductive, and insulating 2D material inks can be produced with scalable techniques and are suitable for the fabrication of fully printed devices on low-cost and biodegradable paper substrates. However, 2D material only and fully printed diodes on paper have not yet been reported. Here, we demonstrate fully inkjet-printed 2D material-based diodes on paper using metal-insulator-semiconductor and metal-insulator-metal-semiconductor architectures. Water-based graphene and MoS2 inks, prepared by liquid-phase exfoliation, are used for the metallic and insulating films, while electrochemical exfoliation is used to produce the semiconducting MoS2 ink. The highest forward-to-reverse current ratio obtained is 330 (at ±2 V), while the forward current density is 1 mA/cm2 (at 1 V), making the diode performance comparable to the best solution-processed diodes reported so far. However, in contrast to previous works, fabrication occurs entirely at room temperature and ambient pressure, without using high-pressure sputtering, thermal evaporation, and any precious metal ink. The devices maintain stable performance under bending up to strain of 4% over 10,000 cycles. Finally, the diodes are successfully integrated with other 2D-material based electrical components to realize fully printed RC circuits, differentiators, integrators, and AC-to-DC converters onto paper, hence demonstrating the suitability of our approach for sustainable and disposable integrated circuits.

2D materials↗
DOE OSTI2025

Tuning the Selectivity of Carboxylic Acid–Based Eutectic Solvents for the Dissolution and Electrochemical Separation of Metal Oxides

Extracting metals from natural resources and recovering from waste materials with less-hazardous solvents is essential for sustainable technological advancements. The commonly employed method utilizes harsh chemicals for metal dissolution and the ensuing separation. Here, in this study, we examined the potential of eutectic solvents (types III and IV) as alternative media for the selective dissolution of metals and metal oxides and their subsequent electrochemical separation. Notably, type III eutectics composed of betaine:acetic acid and triazole:lactic acid exhibited excellent solubility for cobalt oxide (24.1 g·L –1 ) and copper oxide (30.5 g·L –1 ), respectively. In comparison, the type IV eutectic mixture of Ca(NO 3 ) 2 ·4H 2 O:acetic acid demonstrated the highest conductivity and lowest viscosity with solubility for both copper oxide (6.1 g·L –1 ) and metallic copper (5.4 g·L –1 from a used electronic circuit). Using a Ca(NO 3 ) 2 ·4H 2 O:acetic acid mixture, copper was selectively dissolved from a waste printed circuit board and subsequently electrodeposited onto a nickel electrode. These findings highlight the tunability of DESs for the selective recovery of metals from electronic waste, offering a promising approach for sustainable metal recycling and resource recovery.

electrodeposition↗
DOE OSTI2024

High Precision, High Frequency Printed Antennas

An emerging trend in advanced manufacturing is printed electronics and sensors. The ability to print customized electronics and sensors integrated into functional packages is a growing need within a variety of growing markets such as smart manufacturing, internet of things (IoT), and the small satellite industry. Both Oak Ridge National Laboratory (ORNL) and the MITRE Corporation have seedling research efforts evaluating the potential for future printed electronic systems. High frequency, wide-bandwidth phased array antennas (i.e. >45 GHz) open the door to new applications. However, such sensors require currently prohibitively small feature sizes for commercial 3D printing technologies along with increasing challenges with connecting the driving electronics to such features. An additional finding with related advanced manufacturing challenges is the rapid production of 3D additive connectors for integration with commercial printed circuit boards (PCBs), primarily for advanced in-circuit inspection techniques. This work is developing additive manufacturing processes for producing connected and conductive fine scale 3D features. The primary focus was on aerosol-jet printing (AJP), which has a small minimum resolution (<50 µm) but is traditionally printed flat with small height/width aspect ratios <<1, and developing controls to enable fully 3D, high aspect ratio, and unsupported features. In Phase 1 of this effort, baselines of process performance were characterized, and test coupons produced for both ultra-high frequency antennas and microstructures to support reverse engineering of PCBs. In Phase 2, these efforts will be extended for system demonstration of ultra-high frequency antenna arrays, as well as reverse engineering circuitry for dense PCBs.

42 ENGINEERING↗
DOE OSTI2024

Power Layout Design of a GaN HEMTs-Based High-Power High-Efficiency Three-Level ANPC Inverter for 800 V DC Bus System

Multiple commutation paths exist for switching devices in a three-level active neutral point clamped (3L-ANPC) inverter operation based on the selected switching state and current direction. In addition, the capacitive coupling path of the nonswitching device is a key design aspect for enabling high voltage and high current operation of gallium nitride (GaN) switches in 3L-ANPC topology. A comprehensive study of the switching transient events of inner, outer, and clamping devices of 3L-ANPC is presented in this article. The commutation mechanisms for worst-case transient voltage overshoots (TVOs) are identified. A simplified equivalent circuit model is presented to determine the design criteria for the power layout structure's parasitic inductances. A power layout strategy satisfying the design criteria is then proposed using an insulated metal substrate power printed circuit board (PCB) to enable efficient high-power operation. The proposed design minimizes the commutation and capacitive coupling path inductances to 6 nH and 11.5 nH, respectively. This enables the fast switching operation of GaN HEMTs at 800 V dc, 36 A with a low TVO of 31% verified through experimental three-level double pulse test results. Experimental evaluation of a three-phase 3L-ANPC hardware prototype based on the proposed power layout shows 99% efficiency at 800 V, 9.5 kVA and 50 kHz switching frequency. The proposed design achieves a low case-to-ambient thermal resistance of 2.3 °C/W.

42 ENGINEERING↗
DOE OSTI2023

BICEP Array: 150 GHz Detector Module Development

The Background Imaging of Cosmic Extragalactic Polarization (BICEP)/Keck (BK) collaboration is currently leading the quest for the highest-sensitivity measurements of the polarized cosmic microwave background (CMB) anisotropies on a degree scale with a series of cryogenic telescopes, of which BICEP Array (BA) is the latest Stage-3 upgrade with a total of ~ 32,000 detectors. The instrument comprises 4 receivers spanning 30–270 GHz, with the low-frequency 30/40 GHz deployed to the South Pole Station in late 2019. The full complement of receivers is forecast to set the most stringent constraints on the tensor-to-scalar ratio r. Building on these advances, the overarching small-aperture telescope concept is already being used as the reference for further Stage-4 experiment design. This paper describes the development of the BICEP Array 150 GHz detector module and its fabrication requirements, with highlights on the high-density time division multiplexing (TDM) design of the cryogenic circuit boards. The low-impedance wiring required between the detectors and the frst stage of superconducting quantum interference device amplifers is crucial to maintaining a stable bias current on the detectors. Here, a novel multilayer FR4 Printed Circuit Board with superconducting traces, capable of reading out up to 648 detectors, is detailed along with its validation tests. An ultra-high-density TDM detector module concept we developed for a CMB-S4-like experiment that allows up to 1920 detectors to be read out is also presented. TDM has been chosen as the detector readout technology for the Cosmic Microwave Background Stage-4 (CMB-S4) experiment based on its proven low-noise performance, predictable costs, and overall maturity of the architecture. The heritage for TDM is rooted in mm- and sub-mm-wave experiments dating back 20 years and has since evolved to support a multiplexing factor of 64x in Stage-3 experiments.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2023

PRINTED, PLANAR MICROWAVE CONNECTOR WITH MULTIPLE SIGNAL LINES

Microwave connectors with a planar geometry have been demonstrated using additive manufacturing techniques. This planar form factor is expected to enable connectors to be integrated directly with other components onto a printed circuit board. The connectors were developed with multiple signal lines that will increase the density of signal connections to PCBs, eliminating the physical constraints of single-signal COTS microwave connectors. This work developed electromagnetic models (using Ansys HFSS) of these planar connectors to predict performance and optimize connector design. Materials and printing processes were developed to fabricate the connectors based on high-temperature PEEK thermoplastics. The multiple signal connectors were designed to operate over the 1-6GHz band and are built upon the single signal printed planar geometry connector introduced in a previous paper [1].

Additive Manufacturing↗
DOE OSTI2025

Obtaining Real Production Data Through On-Component Printed SIR Patterns

Cleanliness validation of printed circuit assemblies has become increasingly important as electronic assemblies become smaller, denser, and more challenging to clean, prompting an increase in reliance in custom solutions. With increasingly fast paced development cycles, long lead times and costs of quality custom surrogate test boards become prohibitive in obtaining cleanliness data that is a true representative of the final product. In this study, aerosol jet printing, an additive manufacturing technology for electronics, was used to manufacture surface insulation resistance (SIR) test structures that were evaluated on their ability to detect cleanliness defects and remain stable when clean, as well as their survivability to standard electronics wash processes. Additionally, in an effort to further increase the agility of true product testing, SIR test structures were printed directly onto ball-grid-arrays (BGAs) and tested the survivability of conformally printed leads for data acquisition. SIR test structures displayed good wash survivability on standard FR4 and BGAs, including wraparounds for on-component prints, and high sensitivity to cleanliness defects. The presented results demonstrate the feasibility of printed SIR structures as a quick-turn, highly customizable solution for wash validation with potential for increased fidelity cleanliness testing.

SIR, Additive Manufacturing, Printed Electronics, ↗
DOE OSTI2022

Self-Sensing, Stretchable, Active Circuit Arrays: Liquid Metal Paste as a Combination Interconnect and Strain Sensor

Stretchable electrical interconnects and substrate materials are increasingly used to create flexible and con-formable electronic systems for soft robotics, smart textiles, and wearable devices. Wires fabricated using composite or liquid conductive inks encapsulated in silicone enable high strain and are mechanically robust. The resistance of these inter-connects increases with strain, which can present challenges for power delivery and signaling among electronic components. However, this effect can be used directly to estimate strain within a stretchable circuit without the need for additional sensor components. In this work, we present an approach for fabricating fully-stretchable, multi-layer active circuit arrays in silicone using liquid metal paste interconnects, in which power and data wires are re-purposed as strain sensors to estimate substrate deformation. As a proof-of-principle, we demonstrate a 3×3 active circuit array that self-senses relative voltage supply at each node to estimate deformation and consumes less than 10 mA per node. Each node is digitally addressable and performs both analog measurement and digital conversion. All interconnects are fabricated using liquid metal paste, and power, data, and sensing are performed over a shared, four-wire interface in this multi-layer stretchable printed circuit board.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2023

Online Monitoring of Medium Voltage Cable Systems with Spread Spectrum Time Domain and Frequency Domain Reflectometry

In-service failures of wave energy convertor (WEC) cable systems can have a significant cost and power availability impact. Close parallel research 2019 data showed > 1B£ and 9 Terra-Watt-Hours associated with global off-shore wind (OSW) cable failures (Strang-Moran 2020). OSW is a closely related technology but currently is significantly cheaper than WEC technology. For wave energy to compete, the problem of reliable cable transmission must be mitigated. This project develops isolation technology to allow online high frequency reflectometry testing of medium voltage cables (1 to 10 kV and higher) without arcing or damage to the test instrument. Online spread spectrum time domain reflectometry (SSTDR) testing has been established for low voltage cable systems in the aircraft and rail industry and the ability to detect and locate cable flaws of interest is well understood. Extending reflectometry testing to medium voltage systems could enable detection of cable damage before failures occur thereby allowing repair and replacement of damaged cable segments to be scheduled and managed. The seedling project succeeded to pass and receive high frequency SSTDR signals onto a cable up to 1 kV using a parallel trace isolation circuit board that can be connected onto the test cable. The approach used a novel circuit design for which an invention disclosure has been filed. A proposed sapling project would extend the technology toward the higher operating voltages used by WEC systems, thereby enabling online SSTDR cable monitoring. The goal of the seedling project was to extend the capability of the ARENA cable/motor test bed to address medium voltages and to develop a high pass filter isolation architecture to protect the reflectometry instrument from the low frequency (DC – 60 Hz) line voltage while allowing the high frequency diagnostic signal to pass to and from the test instrument to the live line. Initial efforts focused on passive LCR filter circuits to reduce 60 Hz levels below 10 volts from a 10 kV line while allowing the MHz high frequency chirps to pass onto the cables and for mV signals to be detected. We discovered that the parasitic loss behavior of real high voltage components precluded this approach from working. An alternate approach was adapted for the electric field to couple between two parallel traces on a printed circuit board much like a radio-frequency coupler. The challenge here was and is to have the parallel traces close enough to each other to effectively pass the high frequency chirp onto the live line and receive any reflected signal from any encountered impedance change along the cable. This reflected signal will be in the mV range. The traces however must be far enough apart to not allow arcing on the board. A design with 3 mm spacing was determined to allow the high frequency signal to pass onto the live line and receive the mV signal back into the instrument while reducing the 60 Hz voltage amplitude by >80 dB (more than a factor of 10,000) without allowing arcing from across the parallel traces. This was confirmed by simulation and test.

16 TIDAL AND WAVE POWER↗
DOE OSTI2020

Busbar Design and Optimization for Voltage Overshoot Mitigation of a Silicon Carbide High-Power Three-Phase T-Type Inverter

The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Lastly, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies.

42 ENGINEERING↗
DOE OSTI2025

PSEC5 Physical Verification

Ultra-Fast timing detectors, having a time resolution of 10pSec or less, are becoming increasingly important for many scientific disciplines, including High Energy Physics, Nuclear Physics, Medical Imaging and more. When developing ultra-fast detectors such as MCPs, LAPPDs, LGADs, SNSPDs, it is necessary to have access to a readout system that is low power, can support many channels and is cost effective. The PSEC5 chip was an application specific integrated circuit (ASIC) developed by the pioneering group of Prof. Henry Frisch at University of Chicago and micro electronic engineers at Fermi National Accelerator Laboratory. Three boards were designed, two to implement the readout system for an LAPPD and one to only characterize the PSEC1 chip. The main goal of the project shifted to setting up a testing environment to focus on the characterization of the chip. My student and I tested and characterized this ASIC using the third chip-on-board printed circuit board. Results show the successful fabrication and operation of some of the key building blocks and lead to the suggestions on modification for the second iteration of the chip.

Rico Aniles, H. D. [Unlisted]↗