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DOE OSTI2024

All-optical image denoising using a diffractive visual processor

Abstract Image denoising, one of the essential inverse problems, targets to remove noise/artifacts from input images. In general, digital image denoising algorithms, executed on computers, present latency due to several iterations implemented in, e.g., graphics processing units (GPUs). While deep learning-enabled methods can operate non-iteratively, they also introduce latency and impose a significant computational burden, leading to increased power consumption. Here, we introduce an analog diffractive image denoiser to all-optically and non-iteratively clean various forms of noise and artifacts from input images – implemented at the speed of light propagation within a thin diffractive visual processor that axially spans <250 × λ, where λ is the wavelength of light. This all-optical image denoiser comprises passive transmissive layers optimized using deep learning to physically scatter the optical modes that represent various noise features, causing them to miss the output image Field-of-View (FoV) while retaining the object features of interest. Our results show that these diffractive denoisers can efficiently remove salt and pepper noise and image rendering-related spatial artifacts from input phase or intensity images while achieving an output power efficiency of ~30–40%. We experimentally demonstrated the effectiveness of this analog denoiser architecture using a 3D-printed diffractive visual processor operating at the terahertz spectrum. Owing to their speed, power-efficiency, and minimal computational overhead, all-optical diffractive denoisers can be transformative for various image display and projection systems, including, e.g., holographic displays.

36 MATERIALS SCIENCE↗

DOE OSTI2026

Realization of fermionic Laughlin state on a quantum processor

Strongly correlated topological phases of matter are central to modern condensed matter physics and quantum information technology but often challenging to probe and control in material systems. The experimental difficulty of accessing these phases has motivated the use of engineered quantum platforms for simulation and manipulation of exotic topological states. Among these, the Laughlin state stands as a cornerstone for topological matter, embodying fractionalization, anyonic excitations, and incompressibility. Although its bosonic analogs have been realized on programmable quantum simulators, a genuine fermionic Laughlin state has yet to be demonstrated on a quantum processor. Here, we realize the ν = 1/3 fermionic Laughlin state on IonQ’s trapped-ion quantum computer using an efficient and scalable Hamiltonian variational ansatz with 369 two-qubit gates on a 16-qubit circuit. Employing symmetry-verification error mitigation, we extract key observables that characterize the Laughlin state, including correlation hole, bulk-edge correspondence, and topological entanglement entropy, with strong agreement to exact diagonalization benchmarks. This work demonstrates an end-to-end workflow to simulate material-intrinsic topological orders and provides a starting point to explore its dynamics and excitations on digital quantum processors.

Shen, Lingnan [Univ. of Washington, Seattle, WA (U↗

DOE OSTI2024

Extending the computational reach of a superconducting qutrit processor

Quantum computing with qudits is an emerging approach that exploits a larger, more connected computational space, providing advantages for many applications, including quantum simulation and quantum error correction. Nonetheless, qudits are typically afflicted by more complex errors and suffer greater noise sensitivity which renders their scaling difficult. In this work, we introduce techniques to tailor arbitrary qudit Markovian noise to stochastic Weyl–Heisenberg channels and mitigate noise that commutes with our Clifford and universal two-qudit gate in generic qudit circuits. We experimentally demonstrate these methods on a superconducting transmon qutrit processor, and benchmark their effectiveness for multipartite qutrit entanglement and random circuit sampling, obtaining up to 3× improvement in our results. To the best of our knowledge, this constitutes the first-ever error mitigation experiment performed on qutrits. Our work shows that despite the intrinsic complexity of manipulating higher-dimensional quantum systems, noise tailoring and error mitigation can significantly extend the computational reach of today’s qudit processors.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2022

A quantum processor based on coherent transport of entangled atom arrays

The ability to engineer parallel, programmable operations between desired qubits within a quantum processor is key for building scalable quantum information systems. In most state-of-the-art approaches, qubits interact locally, constrained by the connectivity associated with their fixed spatial layout. Here we demonstrate a quantum processor with dynamic, non-local connectivity, in which entangled qubits are coherently transported in a highly parallel manner across two spatial dimensions, between layers of single- and two-qubit operations. Our approach makes use of neutral atom arrays trapped and transported by optical tweezers; hyperfine states are used for robust quantum information storage, and excitation into Rydberg states is used for entanglement generation. We use this architecture to realize programmable generation of entangled graph states, such as cluster states and a seven-qubit Steane code state. Furthermore, we shuttle entangled ancilla arrays to realize a surface code state with thirteen data and six ancillary qubits and a toric code state on a torus with sixteen data and eight ancillary qubits. Finally, we use this architecture to realize a hybrid analogue–digital evolution and use it for measuring entanglement entropy in quantum simulations, experimentally observing non-monotonic entanglement dynamics associated with quantum many-body scars. Realizing a long-standing goal, these results provide a route towards scalable quantum processing and enable applications ranging from simulation to metrology.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2023

Measurement-induced entanglement and teleportation on a noisy quantum processor

Measurement has a special role in quantum theory: by collapsing the wavefunction, it can enable phenomena such as teleportation and thereby alter the ‘arrow of time’ that constrains unitary evolution. When integrated in many-body dynamics, measurements can lead to emergent patterns of quantum information in space–time that go beyond the established paradigms for characterizing phases, either in or out of equilibrium. For present-day noisy intermediate-scale quantum (NISQ) processors, the experimental realization of such physics can be problematic because of hardware limitations and the stochastic nature of quantum measurement. Here we address these experimental challenges and study measurement-induced quantum information phases on up to 70 superconducting qubits. By leveraging the interchangeability of space and time, we use a duality mapping to avoid mid-circuit measurement and access different manifestations of the underlying phases, from entanglement scaling to measurement-induced teleportation. We obtain finite-sized signatures of a phase transition with a decoding protocol that correlates the experimental measurement with classical simulation data. The phases display remarkably different sensitivity to noise, and we use this disparity to turn an inherent hardware limitation into a useful diagnostic. Our work demonstrates an approach to realizing measurement-induced physics at scales that are at the limits of current NISQ processors.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2023

Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors

Abstract Recent studies in quantum computing have shown that quantum error correction with large numbers of physical qubits are limited by ionizing radiation from high-energy particles. Depending on the physical setup of the quantum processor, the contribution of muons from cosmic sources can constitute a significant fraction of these interactions. As most of these muons are difficult to stop, we perform a conceptual study of a two-layer silicon pixel detector to tag their hits on a solid-state quantum processor instead. With a typical dilution refrigerator geometry model, we find that efficiencies greater than 50% are most likely to be achieved if at least one of the layers is operated at the deep-cryogenic (<1 K) flanges of the refrigerator. Following this finding, we further propose a novel research program that could allow the development of silicon pixel detectors that are fast enough to provide input to quantum error correction algorithms, can operate at deep-cryogenic temperatures, and have very low power consumption.

Instruments & Instrumentation↗

DOE OSTI2020

Probing quantum processor performance with pyGSTi

PyGSTi is a Python software package for assessing and characterizing the performance of quantum computing processors. It can be used as a standalone application, or as a library, to perform a wide variety of quantum characterization, verification, and validation (QCVV) protocols on as-built quantum processors. In this work, we outline pyGSTi's structure, and what it can do, using multiple examples. We cover its main characterization protocols with end-to-end implementations. These include gate set tomography, randomized benchmarking on one or many qubits, and several specialized techniques. We also discuss and demonstrate how power users can customize pyGSTi and leverage its components to create specialized QCVV protocols and solve user-specific problems.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2023

Simulating noise on a quantum processor: interactions between a qubit and resonant two-level system bath

Material defects fundamentally limit the coherence times of superconducting qubits, and manufacturing completely defect-free devices is not yet possible. Therefore, understanding the interactions between defects and a qubit in a real quantum processor design is essential. We build a model that incorporates the standard tunneling model, the electric field distributions in the qubit, and open quantum system dynamics, and draws from the current understanding of two-level system (TLS) theory. Specifically, we start with one million TLSs distributed on the surface of a qubit and pick the 200 systems that are most strongly coupled to the qubit. We then perform a full Lindbladian simulation that explicitly includes the coherent coupling between the qubit and the TLS bath to model the time dependent density matrix of resonant TLS defects and the qubit. We find that the 200 most strongly coupled TLSs can accurately describe the qubit energy relaxation time. This work confirms that resonant TLSs located in areas where the electric field is strong can significantly affect the qubit relaxation time, even if they are located far from the Josephson junction (JJ). Similarly, a strongly-coupled resonant TLS located in the JJ does not guarantee a reduced qubit relaxation time if a more strongly coupled TLS is far from the JJ. In addition to the coupling strengths between TLSs and the qubit, the model predicts that the geometry of the device and the TLS relaxation time play a significant role in qubit dynamics. Our work can provide guidance for future quantum processor designs with improved qubit coherence times.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2026

A cryogenic muon tagging system based on kinetic inductance detectors for superconducting quantum processors

Ionizing radiation has emerged as a potential limiting factor for superconducting quantum processors, inducing quasiparticle bursts and correlated errors that challenge fault-tolerant operation. Atmospheric muons are particularly problematic due to their high energy and penetration power, making passive shielding ineffective. Therefore, monitoring the real-time muon flux is crucial to guide the development of alternative error-correction or mitigation strategies. We present the design, simulation, and first operation of a cryogenic muon-tagging system based on kinetic inductance detectors (KIDs), developed as a stand-alone cryogenic particle-tagging module for superconducting quantum processors. The system consists of two KIDs arranged in a vertical stack and operated at ∼20 mK. Monte Carlo simulations based on Geant4 guided the prototype design and provided reference expectations for muon-tagging efficiency and accidental coincidences due to ambient γ-rays. We observed a muon-induced coincidence rate among the top and bottom detectors of (192 ± 9) $\times\,10^{-3}$ events s$^{−1}$, in excellent agreement with the Monte Carlo prediction. The prototype achieves a muon-tagging efficiency of about 90% with negligible dead time. These results demonstrate the feasibility of operating a muon-tagging system at millikelvin temperatures and represent a key step toward the integration of cryogenic veto systems with multi-qubit chips to mitigate muon-induced errors.

Mariani, Ambra [INFN, Rome] (ORCID:000000028184857↗

DOE OSTI2019

Simulations of subatomic many-body physics on a quantum frequency processor

Simulating complex many-body quantum phenomena is a major scientific impetus behind the development of quantum computing, and a range of technologies are being explored to address such systems. We present the results of the largest photonics-based simulation to date, applied in the context of subatomic physics. Using an all-optical quantum frequency processor, the ground-state energies of light nuclei including the triton ( 3 H), 3 He, and the alpha particle ( 4 He) are computed. Complementing these calculations and utilizing a 68-dimensional Hilbert space, our photonic simulator is used to perform subnucleon calculations of the two- and three-body forces between heavy mesons in the Schwinger model. Furthermore, this work is a first step in simulating subatomic many-body physics on quantum frequency processors—augmenting classical computations that bridge scales from quarks to nuclei.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2021

Non-Gaussian photonic state engineering with the quantum frequency processor

Non-Gaussian quantum states of light are critical resources for optical quantum information processing, but methods to generate them efficiently remain challenging to implement. Here we introduce a generic approach for non-Gaussian state production from input states populating discrete frequency bins. Based on controllable unitary operations with a quantum frequency processor, followed by photon-number-resolved detection of ancilla modes, our method combines recent developments in both frequency-based quantum information and non-Gaussian state preparation. Leveraging and refining the K-function representation of quantum states in the coherent basis, we develop a theoretical model amenable to numerical optimization and, as specific examples, design quantum frequency processor circuits for the production of Schrödinger cat states, exploring the performance tradeoffs for several combinations of ancilla modes and circuit depth. Our scheme provides a valuable framework for producing complex quantum states in frequency bins, paving the way for single-spatial-mode, fiber-optic-compatible non-Gaussian resources.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2024

Modular Quantum Processor with an All-to-All Reconfigurable Router

Superconducting qubits provide a promising approach to large-scale fault-tolerant quantum computing. However, qubit connectivity on a planar surface is typically restricted to only a few neighboring qubits. Achieving longer-range and more flexible connectivity, which is particularly appealing in light of recent developments in error-correcting codes, however, usually involves complex multilayer packaging and external cabling, which is resource intensive and can impose fidelity limitations. Here, we propose and realize a high-speed on-chip quantum processor that supports reconfigurable all-to-all coupling with a large on-off ratio. We implement the design in a four-node quantum processor, built with a modular design comprising a wiring substrate coupled to two separate qubit-bearing substrates, each including two single-qubit nodes. We use this device to demonstrate reconfigurable controlled-𝑍 gates across all qubit pairs, with a benchmarked average fidelity of 96.00% ± 0.08% and best fidelity of 97.14% ± 0.07%, limited mainly by dephasing in the qubits. We also generate multiqubit entanglement, distributed across the separate modules, demonstrating GHZ-3 and GHZ-4 states with fidelities of 88.15% ± 0.24% and 75.18% ± 0.11%, respectively. This approach promises efficient scaling to larger-scale quantum circuits and offers a pathway for implementing quantum algorithms and error-correction schemes that benefit from enhanced qubit connectivity.

Quantum circuits↗

DOE OSTI2024

Circuit-Based Leakage-to-Erasure Conversion in a Neutral-Atom Quantum Processor

Atom-loss errors are a major limitation of current state-of-the-art neutral-atom quantum computers and pose a significant challenge for scalable systems. In a quantum processor with cesium atoms, we demonstrate proof-of-principle circuit-based conversion of this form of leakage error to erasure errors via leakage-detection units (LDUs), which nondestructively map information about the presence or absence of the qubit onto the state of an ancilla. We benchmark the performance of the LDU using a three-outcome low-loss state-detection method and find that the LDU detects atom-loss errors with approximately 93.4% accuracy, limited by technical imperfections of our apparatus. We further compile and execute a SWAP LDU, wherein the roles of the original data atom and ancilla atom are exchanged under the action of the LDU, providing “free refilling” of atoms in the case of atom loss. This circuit-based leakage-to-erasure error conversion is a critical component of a neutral-atom quantum processor where the quantum information may significantly outlive the lifetime of any individual atom in the quantum register. Finally, we demonstrate that LDUs may also be used to handle other forms of leakage errors where population moves to states outside of the computational subspace.

Chow, Matthew N. H. [Sandia National Laboratories ↗

DOE OSTI2025

Probing Curved Spacetime with a Distributed Atomic Processor Clock

Quantum dynamics on curved spacetime has never been directly probed beyond the Newtonian limit. Although we can describe such dynamics theoretically, experiments would provide empirical evidence that quantum theory holds even in this extreme limit. The practical challenge is the minute spacetime curvature difference over the length scale of the typical extent of quantum effects. Here, we propose a quantum network of alkaline earth (like) atomic processors for constructing a distributed quantum state that is sensitive to the differential proper time between its constituent atomic processor nodes, implementing a quantum observable that is affected by post-Newtonian curved spacetime. Conceptually, we propose to delocalize one clock between three locations by encoding the presence or absence of a clock into the state of the local atoms. By separating three atomic nodes over approximately kilometer-scale elevation differences and distributing one clock between them via a 𝑊 state, we demonstrate that the curvature of spacetime is manifest in the interference of the three different proper times that give rise to three distinct beat notes in our nonlocal observable. We further demonstrate that 𝑁-atom entanglement within each node enhances the interrogation bandwidth by a factor of 𝑁. We discuss how our proposed system can probe new facets of fundamental physics, such as the linearity, unitarity, and probabilistic nature of quantum theory on curved spacetime. Our protocol combines several recent advances with neutral atom and trapped ions to realize a novel quantum probe of gravity uniquely enabled by quantum networks.

Covey, Jacob P. [Univ. of Illinois at Urbana-Champ↗

DOE OSTI2023

An FPGA-Based Neuromorphic Processor with All-to-All Connectivity

Neuromorphic computing is a promising paradigm for future energy-efficient computing. At present, however, it is in its nascent stages—most hardware implementations are research-grade, commercial products are not available, and the software tools are not production-ready. The lack of hardware and software tools makes neuromorphic computing inaccessible to researchers around the globe. To this extent, we intend to build a low-cost, open-source, FPGA-based digital neuromorphic processor that can be used by researchers worldwide. In this paper, we present a preliminary implementation of the processor on a Xilinx Artix-7 FPGA using SystemVerilog. Our implementation supports the integrate-and-fire neuron with two parameters each for neurons and synapses. It also features all-to-all connectivity among neurons on the hardware. We test our implementation on four cases: bars and stripes datasets, shortest path algorithm, logic gates, and 8-3 encoder. We also perform a scalability study to understand the resource utilization of the FPGA as the number of all-to-all connected neurons increases. With our implementation, the Artix- 7 supports 65 neurons with all-to-all connectivity. Moreover, all the test cases mentioned above achieve 100% accuracy.

Maheshwari, Disha↗

DOE OSTI2017

Towards Highly Scalable Ab Initio Molecular Dynamics (AIMD) Simulations on the Intel Knights Landing Manycore Processor

The Ab Initio Molecular Dynamics (AIMD) method allows scientists to treat the dynamics of molecular and condensed phase systems while retaining a first-principles-based description of their interactions. This extremely important method has tremendous computational requirements, because the electronic Schr¨odinger equation, approximated using Kohn-Sham Density Functional Theory (DFT), is solved at every time step. With the advent of manycore architectures, application developers have a significant amount of processing power within each compute node that can only be exploited through massive parallelism. A compute intensive application such as AIMD forms a good candidate to leverage this processing power. In this paper, we focus on adding thread level parallelism to the plane wave DFT methodology implemented in NWChem. Through a careful optimization of tall-skinny matrix products, which are at the heart of the Lagrange multiplier and nonlocal pseudopotential kernels, as well as 3D FFTs, our OpenMP implementation delivers excellent strong scaling on the latest Intel Knights Landing (KNL) processor. We assess the efficiency of our Lagrange multiplier kernels by building a Roofline model of the platform, and verify that our implementation is close to the roofline for various problem sizes. Finally, we present strong scaling results on the complete AIMD simulation for a 64 water molecules test case, that scales up to all 68 cores of the Knights Landing processor.

Environmental Molecular Sciences Laboratory↗

DOE OSTI2022

Benchmarking Quantum Processor Performance through Quantum Distance Metrics Over An Algorithm Suite

Quantum computing is poised to solve computational paradigms that classical computing could never feasibly reach. Tasks such as prime factorization to Quantum Chemistry are examples of classically difficult problems that have analogous algorithms that are sped up on quantum computers. To attain this computational advantage, we must first traverse the noisy intermediate scale quantum (NISQ) era, in which quantum processors suffer from compounding noise factors that can lead to unreliable algorithm induction producing noisy results. We describe QASMBench, a suite of QASM-level (Quantum assembly language) benchmarks that challenge all realisable angles of quantum processor noise. We evaluate a large portion of these algorithms by performing density matrix tomography on 14 IBMQ Quantum devices.

Stein, Samuel A.↗

DOE OSTI2021

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Furthermore, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

42 ENGINEERING↗