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Benefits of Force Limiting Vibration Testing

Force limited random vibration testing is used at NASA John Glenn Research Center (formerly NASA Lewis Research Center) for qualifying aerospace hardware for flight. The benefit of force limiting testing is that it limits overtesting of flight hardware, by controlling input force and acceleration from the shaker (dual control) to the test article. The purpose of force limiting is to replicate the test article resonant response for the actual flight mounting condition. The force limiting testing technology has been implemented at the Jet Propulsion Laboratory for the past 10 years on various spacecraft testing programs. The Cassini mission to Saturn, most notably, utilized force limiting vibration testing as part of the spacecraft system level vibration testing. NASA John Glenn Research Center is responsible for microgravity combustion and fluid science research on the Shuttle and the International Space Station. Qualification testing of delicate and vibration sensitive science instrumentation is particularly challenging to successfully qualify for flight. In order to facilitate the testing process, force limiting has been implemented to minimize overtesting of flight hardware. This paper will address recent flight camera testing (qualification random vibration and strength testing) for the Combustion Module-2 mission and the impact of Semi-empirical Method force limits.

McNelis, Mark E.

Quantifying parameters for Bayesian prior assumptions when estimating the probability of failure of software

Software reliability has become increasingly important, especially in life-critical situations. The ability to measure the results of testing and to quantify software reliability is needed. If this is accomplished, a certain minimum amount of reliability for a piece of software can be specified, and testing and/or other analysis may be done until that minimum number has been attained. There are many models for estimating software reliability. The accuracy of these models has been challenged and many revisions for the models and recalibration techniques have been devised. Of particular interest is the method of estimating the probability of failure of software when no failures have yet occurred in its current version as described by Miller. This model uses black box testing with formulae based on Bayesian estimation. The focus is on three interrelated issues: estimating the probability of failure when testing has revealed no errors; modifying this estimation when the input use distribution does not match the test distribution; and combining the results from random testing with other relevant information to obtain a possibly more accurate estimate of the probability of failure. Obtaining relevant information about the software and combining the results for a better estimate for the Miller model are discussed.

Long, Jacquelyn E.

Recent Status of SIM Lite Astrometric Observatory Mission: Flight Engineering Risk Reduction Activities

The SIM Lite Astrometric Observatory is a mission concept for a space-borne instrument to perform micro-arc-second narrow-angle astrometry to search 60 to 100 nearby stars for Earth-like planets, and to perform global astrometry for a broad astrophysics program. The instrument consists of two Michelson stellar interferometers and a telescope. The first interferometer chops between the target star and a set of reference stars. The second interferometer monitors the attitude of the instrument in the direction of the target star. The telescope monitors the attitude of the instrument in the other two directions. The main enabling technology development for the mission was completed during phases A & B. The project is currently implementing the developed technology onto flight-ready engineering models. These key engineering tasks will significantly reduce the implementation risks during the flight phases C & D of the mission. The main optical interferometer components, including the astrometric beam combiner, the fine steering optical mechanism, the path-length-control and modulation optical mechanisms, focal-plane camera electronics and cooling heat pipe, are currently under development. Main assemblies are built to meet flight requirements and will be subjected to flight qualification level environmental testing (random vibration and thermal cycling) and performance testing. This paper summarizes recent progress in engineering risk reduction activities.

astrometry

Estimating the probability of failure when testing reveals no failures

Formulas for estimating the probability of failure when testing reveals no errors are introduced. These formulas incorporate random testing results, information about the input distribution, and prior assumptions about the probability of failure of the software. The formulas are not restricted to equally likely input distributions, and the probability of failure estimate can be adjusted when assumptions about the input distribution change. The formulas are based on a discrete sample space statistical model of software and include Bayesian prior assumptions. Reusable software and software in life-critical applications are particularly appropriate candidates for this type of analysis.

Miller, Keith W.

An Integrated Analysis-Test Approach

This viewgraph presentation provides an overview of a project to develop a computer program which integrates data analysis and test procedures. The software application aims to propose a new perspective to traditional mechanical analysis and test procedures and to integrate pre-test and test analysis calculation methods. The program also should also be able to be used in portable devices and allows for the 'quasi-real time' analysis of data sent by electronic means. Test methods reviewed during this presentation include: shaker swept sine and random tests, shaker shock mode tests, shaker base driven model survey tests and acoustic tests.

Kaufman, Daniel

NASA/BAE SYSTEMS SpaceWire Effort

This paper discusses the state of the NASA and BAE SYSTEMS developments of SpaceWire. NASA has developed intellectual property that implements SpaceWire in Register Transfer Level (RTL) VHDL for a SpaceWire link and router. This design has been extensively verified using directed tests from the SpaceWire Standard and design specification, as well as being randomly tested to flush out hard to find bugs in the code. The high level features of the design will be discussed, including the support for multiple time code masters, which will be useful for the James Webb Space Telescope electrical architecture. This design is now ready to be targeted to FPGA's and ASICs. Target utilization and performance information will be presented for Spaceflight worthy FPGA's and a discussion of the ASIC implementations will be addressed. In particular, the BAE SYSTEMS ASIC will be highlighted which will be implemented on their .25micron rad-hard line. The chip will implement a 4-port router with the ability to tie chips together to make larger routers without external glue logic. This part will have integrated LVDS drivers/receivers, include a PLL and include skew control logic. It will be targeted to run at greater than 300 MHz and include the implementation for the proposed SpaceWire transport layer. The need to provide a reliable transport mechanism for SpaceWire has been identified by both NASA And ESA, who are attempting to define a transport layer standard that utilizes a low overhead, low latency connection oriented approach that works end-to-end. This layer needs to be implemented in hardware to prevent bottlenecks.

Rakow, Glenn Parker

NASA/BAE Systems SpaceWire Efforts

This paper discusses the state of the NASA and BAE SYSTEMS developments using Spacewire. NASA has developed intellectual property that implements Spacewire in Register Transfer Level VHDL for a Spacewire link and router. This design has been extensively verified using directed tests from the Spacewire Standard and design specification, as well as being randomly tested to flush out hard to find bugs in the code. The high level features of the design will be discussed, including the support for multiple time code masters, which will be useful for the James Webb Space Telescope electrical architecture. This design is now ready to be targeted to FPGA's and ASICs. Target utilization and performance information will be presented for some spaceflight qualified FPGA's and a discussion of the ASIC implementations will be addressed. In particular, the BAE SYSTEMS ASIC will be highlighted which will be implemented in their 0.25 micron rad-hard line. The chip will implement a 4-port router with the ability to tie chips together to make larger routers without external glue logic. This part will have integrated LVDS driver/receivers, include a PLL and include skew control logic. It will be targeted to run at greater than 300 MHz and include the implementation for the proposed Spacewire transport layer. The need to provide a reliable transport mechanism for Spacewire has been identified by both NASA and ESA, who are attempting to define a transport layer standard that utilizes a low overhead, low latency connection oriented approach. The Transport layer needs to be implemented in hardware-to prevent bottlenecks.

Rakow, Glenn Parker

Vibroacoustic study of the NASA Goddard Space Flight Center OSS-1 payload

A comparative evaluation of shuttle liftoff and ground test random response data obtained from the Office of Space Science-1 (OSS-1) pallet payload flown in the cargo bay of STS-3 is presented. The study was initiated to evaluate the possibility that the payload flight vibration response can exceed that occurred during ground test when the ground test acoustic excitation is normalized to the flight acoustic environment. In addition, the analytically derived response from the Vibroacoustic Payload Environment Prediction System (VAPEPS) is compared with OSS-1 ground test results.

Lee, Y. A.

TRIM: AI Guided Random Number Generation for Resource-Constrained IoT Systems

Random numbers often serve as the backbone for many security solutions in diverse domains such as cryptography, side channel leakage prevention, and moving target defense. However, generating true random numbers requires a physical source of entropy (e.g. hardware, quantum, environmental phenomenon) making it difficult to realize at a large scale and at a low cost. On the flip side, pseudorandom number generators (easy to implement) following a specific distribution (e.g. Gaussian) can be easily compromised given a sufficient amount of traces. In this work, we have developed a machine learning-guided generative approach that can be used to create portable, resource-efficient, and cost-effective random number generators with high throughput and true randomness characteristics. We implement the proposed approach as a highly parameterized framework and perform extensive evaluation for different settings. The framework was able to learn from true random sources such as irrational numbers and environmental audio noise and imitate those sources towards generating new good quality random numbers on demand. We have generated more than 1 billion bits and observed robust performance in terms of true randomness metrics obtained from NIST SP 800-22 and FIPS 140-1 randomness test suites achieving a throughput of up to 142.85 Mbps. Compared to the state-of-the-art (SOTA) technique, the iso-cost setup of our framework can achieve more than 500 Mbps in a distributed setting. We have evaluated the efficacy of running the true randomness imitation AI models on target edge devices such as Raspberry Pi 4 (Model B), Nvidia Jetson Nano, Nvidia Jetson Orin Nano and Nvidia Jetson Xavier. We have also looked at the security of the TRIM framework itself against different adversarial threat models.

Cybersecurity

Vertical Axis Rotational Motion Cues in Hovering Flight Simulation

A previous study that examined how yaw motion affected a pilot's ability to perform realistic hovering flight tasks indicated that any amount of pure yaw motion had little-to-no effect on pilot performance or opinion. In that experiment, pilots were located at the vehicle's center of rotation; thus lateral or longitudinal accelerations were absent. The purpose of the new study described here was to investigate further these unanticipated results for additional flight tasks, but with the introduction of linear accelerations associated with yaw rotations when the pilot is not at the center of rotation. The question of whether a yaw motion degree-of-freedom is necessary or not is important to government regulators who specify what simulator motions are necessary according to prescribed levels of simulator sophistication. Currently, specifies two levels of motion sophistication for flight simulators: full 6-degree-of-freedom and 3-degree-of-freedom. For the less sophisticated simulator, the assumed three degrees of freedom are pitch, roll, and heave. If other degrees of freedom are selected, which are different f rom these three, they must be qualified on a case-by-case basis. Picking the assumed three axes is reasonable and based upon experience, but little empirical data are available to support the selection of critical axes. Thus, the research described here is aimed at answering this question. The yaw and lateral degrees of freedom were selected to be examined first, and maneuvers were defined to uncouple these motions from changes in the gravity vector with respect to the pilot. This approach simplifies the problem to be examined. For this experiment, the NASA Ames Vertical Motion Simulator was used in a comprehensive investigation. The math model was an AH-64 Apache in hover, which was identified from flight test data and had previously been validated by several AH-64 pilots. The pilot's head was located 4.5 ft in front of the vehicle center of gravity, which is representative of the AH-64 pilot location. Six test pilots flew three tasks that were specifically designed to represent a broad class of situations in which both lateral and yaw motion cues may be useful. For the first task, the pilot controlled only the yaw axis and was required to rapidly acquire a North heading from 15 deg yaw offsets to either the East or West. This task allowed for full, or 1:1, motion to be used in all axes (yaw, lateral, and longitudinal). The second task was a 10 sec., 180 deg. pedal turn over a runway, but with the pilot only controlling the yaw degree-of-freedom. The position of the vehicle's center-of-mass remained fixed. This maneuver was taken from a current U.S. Army rotary wing design standard5 and is representative of a maneuver performed for acceptance of military helicopters; however, it does not allow for full 1:1 motion, since the simulator cab cannot rotate 180 deg. The third task required the pilot to perform a rapid 9 ft climb at a constant heading. This task was challenging, because rapid collective lever movement in the unaugmented AH64 results in a substantial yawing moment (due to engine torque) that must be countered by the pilot. This task also had full motion in all axes, but, in this case, the pilot had two axes to control simultaneously, rather than one as in the previous tasks. Four motion configurations were examined for each task: full motion (except for the 180 deg turn, for which the motion system was configured to provide as much motion as possible), full linear with no yaw motion, full yaw with no linear motion, and no motion. Each configuration was flown four times in a randomized test matrix, and the pilots were not informed of the configuration given. Vehicle state data were recorded for objective performance comparisons, and pilots provided subjective comments and ratings. As part of the pilots' evaluation, they were asked to rate the compensation required, the overall fidelity of the motion as compared to real flight, and whether motion was detected or not in each of the six degrees of freedom. In addition, the pilots provided a numerical level-of confidence rating, between 1 and 7, corresponding to how sure they were whether or not motion was present in each degree-of-freedom. The latter rating allow classical signal detection analysis to be performed.

Schroeder, Jeffrey A.

Design guidelines for the testability of microprocessor based logic designs

This paper deals with the issue of designing microprocessor based systems with testability in mind. The ease of eventual testability should be a design consideration from the earliest design stage. Design guidelines with explicit examples for ease of testability are given. The issue of testing microprocessors as contrasted with testing random logic design is addressed, and procedures are delineated for the testability of microprocessors. Microprocessor testability design guidelines are discussed both at the design stage of the microprocessor itself as well as at the stage where the processor is imbedded as a component in a larger system. Specific instances and examples of a collection of design do's and don'ts are provided.

Mathur, F. P.

Integrated active and passive control design methodology for the LaRC CSI evolutionary model

A general design methodology to integrate active control with passive damping was demonstrated on the NASA LaRC CSI Evolutionary Model (CEM), a ground testbed for future large, flexible spacecraft. Vibration suppression controllers designed for Line-of Sight (LOS) minimization were successfully implemented on the CEM. A frequency-shaped H2 methodology was developed, allowing the designer to specify the roll-off of the MIMO compensator. A closed loop bandwidth of 4 Hz, including the six rigid body modes and the first three dominant elastic modes of the CEM was achieved. Good agreement was demonstrated between experimental data and analytical predictions for the closed loop frequency response and random tests. Using the Modal Strain Energy (MSE) method, a passive damping treatment consisting of 60 viscoelastically damped struts was designed, fabricated and implemented on the CEM. Damping levels for the targeted modes were more than an order of magnitude larger than for the undamped structure. Using measured loss and stiffness data for the individual damped struts, analytical predictions of the damping levels were very close to the experimental values in the (1-10) Hz frequency range where the open loop model matched the experimental data. An integrated active/passive controller was successfully implemented on the CEM and was evaluated against an active-only controller. A two-fold increase in the effective control bandwidth and further reductions of 30 percent to 50 percent in the LOS RMS outputs were achieved compared to an active-only controller. Superior performance was also obtained compared to a High-Authority/Low-Authority (HAC/LAC) controller.

Voth, Christopher T.

Improving the Software Development Process Using Testability Research

Software testability is the the tendency of code to reveal existing faults during random testing. This paper proposes to take software testability predictions into account throughout the development process. These predictions can be made from formal specifications, design documents, and the code itself. The insight provided by software testability is valuable during design, coding, testing, and quality assurance. We further believe that software testability analysis can play a crucial role in quantifying the likelihood that faults are not hiding after testing does not result in any failures for the current version.

Voas, Jeffrey M.

Modeling with Scala

The activities and the associated formalisms for modeling and programming have many commonalities. In this paper we emphasize this point of view by modeling two examples in the programming language Scala, which have previously been modeled in the VDM specification language, and the Promela modeling language of the SPIN model checker respectively. The latter Scala model uses an internal DSL for hierarchical state machines, and a simple randomized testing framework exposing the same errors as found with SPIN. We believe, as the examples illustrate, that this use of a modern programming language for modeling is promising, especially if utilizing internal DSLs.

Joshi, Rajeev

Self-Testing Static Random-Access Memory

Proposed static random-access memory for computer features improved error-detecting and -correcting capabilities. New self-testing scheme provides for detection and correction of errors at any time during normal operation - even while data being written into memory. Faults in equipment causing errors in output data detected by repeatedly testing every memory cell to determine whether it can still store both "one" and "zero", without destroying data stored in memory.

Chau, Savio