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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Low-Cost Handle Study for Photovoltaics on Transfer Printed Virtual Substrates

This work expands upon previous research related to transfer printed virtual substrates: a technique for generating low-cost engineered substrates that is not based on wafer reuse. Here, silicon and sapphire are evaluated as candidate low-cost handle materials, validated by metal organic chemical vapor deposition regrowth of GaAs single-junction solar cells. Resulting devices are studied via materials and electrical characterization techniques, including concentration measurements that indicate GaAs//sapphire TPVS open-circuit voltage at >10 suns comparable with identical devices grown on a prime GaAs substrate.

41 EE - Solar Energy Technologies Office (EE-4S)↗
NASA NTRS1993

A Compact Imaging Detector of Polarization and Spectral Content

A new type of image detector will simultaneously analyze the polarization of light at all picture elements in a scene. The integrated Dual Imaging Detector (IDID) consists of a polarizing beam splitter bonded to a charge-coupled device (CCD), with signal-analysis circuitry and analog-to-digital converters, all integrated on a silicon chip. The polarizing beam splitter can be either a Ronchi ruling, or an array of cylindrical lenslets, bonded to a birefringent wafer. The wafer, in turn, is bonded to the CCD so that light in the two orthogonal planes of polarization falls on adjacent pairs of pixels. The use of a high-index birefringent material, e.g., rutile, allows the IDID to operate at f-numbers as high as f/3.5. Other aspects of the detector are discussed.

Rust, D. M.↗
NASA NTRS2000

Technical Challenges in Reliable Microelectronics Packaging of Microelectromechanical Systems (MEMS) for Space Applications

MEMS have shown a significant promise in the last decade for a variety of applications such as air-bag, pressure sensors, accelerometer, microgyro, chemical sensors, artificial nose, etc. Standard semiconductor microelectronics packaging needs the integrated circuits (IC) to be protected from the harsh environment, and provide electrical communication with the other parts of the circuit, facilitate thermal dissipation efficiently, and impart mechanical strength to the silicon die. Microelectronics packaging involves wafer dicing, bonding, lead attachment, encapsulation to protect from the environment, electrical integrity, and package leak tests to assure the reliable IC packaging technology. Active elements or microstructures in MEMS devices often interfaces with the hostile environment where packaging leak tests and testing of such devices using chemical and mechanical parameters will be very difficult and expensive. Packaging of MEMS is significantly complex as they serve to protect from the environment and microstructures interact with the same environment to measure or affect the desired physical or chemical parameters. The most of the silicon circuitry is sensitive to temperature, moisture, magnetic field, light, and electromagnetic interference. The package must then protect the on-board silicon circuitry while simultaneously exposing the microsensor to the effect it measures to assure the packaging technology of MEMS. MEMS technology has a major application in developing a microspacecraft for space systems provided reliability of MEMS packaging technology is sufficiently addressed. This MEMS technology would eventually miniaturize many of the components of the spacecraft to reach the NASA's goal by building faster, cheaper, better, smaller spacecraft to explore the space more effectively. This paper discusses the latest developments in the MEMS technology and challenging technical issues in the packaging of hermetically sealed and non-hermetically sealed MEMS sensor devices for microspacecraft applications.

Ramesham, Rajeshuni↗
NASA NTRS2000

Assessment and Assurance of Microelectronics Packaging Technology of Microelectromechanical Systems (MEMS)

Microelectromechanical systems (MEMS) have shown a significant promise in the last decade for a variety of applications such as air-bag, pressure sensors, accelerometer, microgyro, etc. Standard semiconductor microelectronics packaging needs the integrated circuits to be protected from the harsh environment, and provide electrical communication with the other parts of the circuit, facilitate thermal dissipation efficiently, and impart mechanical strength to the silicon die. Microelectronics packaging involves wafer dicing, bonding, lead attachment, encapsulation to protect from the environment, electrical integrity, and package leak tests to assure the packaging technology. In the case of MEMS the microstructures (active elements) often interfaces with the hostile environment where packaging leak tests and testing of such devices using chemical and mechanical parameters will be very difficult and expensive. Packaging of MEMS is significantly complex as they serve to protect from the environment and microstructures interact with the same environment to measure or affect the desired physical or chemical parameters. The most of the silicon circuitry is sensitive to temperature, moisture, magnetic field, light, and electromagnetic interference. The package must then protect the on-board silicon circuitry while simultaneously exposing the microsensor to the effect it 'measures to assure the MEMS technology by lowering the risk to zero. MEMS technology has a major application in developing a microspacecraft for space systems provided assurance of MEMS technology is sufficiently addressed nondestructively. This technology would eventually miniaturize many of the components of the spacecraft to reach the NASA's safety and mission assurance goal by building faster, cheaper, better, smaller spacecraft to explore the space more effectively by teaming-up with the other NASA centers using the limited resources available. This paper discusses the latest developments in the MEMS technology and challenging issues in the packaging of hermetically sealed and non-hermetically sealed MEMS sensor devices based on silicon, poly-silicon, and other materials for microspacecraft applications considering the space environment and reliability assurance qualification guidelines in perspective. Acknowledgments: The above research work is supported by the NASA Electronics Parts and Packaging Program (NEPP) and performed by the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA under a contract with the NASA - Code Q for the Office of Safety and Mission Assurance Program 323-79.

Ramesham, Rajeshuni↗
NASA NTRS2001

Nanoklystron: A Monolithic Tube Approach to THz Power Generation

The authors propose a new approach to THz power generation: the nanoklystron. Utilizing silicon micromachining techniques, the design and fabrication concept of a monolithic THz vacuum-tube reflex-klystron source is described. The nanoklystron employs a separately fabricated cathode structure composed of densely packed carbon nanotube field emitters and an add-in repeller. The nanotube cathode is expected to increase the current density, extend the cathode life and decrease the required oscillation voltage to values below 100 V. The excitation cavity is based on ridged-waveguide and differs from the conventional cylindrical re-entrant structures found in lower frequency klystrons. A quasi-static field analysis of the cavity and output coupling structure show excellent control of the quality factor and desired field distribution. Output power is expected to occur through an iris coupled matched rectangular waveguide and integrated pyramidal feed horn. The entire circuit is designed so as to be formed monolithically from two thermocompression bonded silicon wafers processed using deep reactive ion etching (DRIE) techniques. To expedite prototyping, a 600 GHz mechanically machined structure has been designed and is in fabrication. A complete numeric analysis of the nanoklystron circuit, including the electron beam dynamics has just gotten underway. Separate evaluation of the nanotube cathodes is also ongoing. The authors will describe the progress to date as well as plans for the immediate implementation and testing of nanoklystron prototypes at 640 and 1250 GHz.

Siegel, Peter H.↗
NASA NTRS1987

Curved channel MCP improvement program

Blowholes and blemishes were determined to start at two stages of manufacturing. Sperical blowholes resulted from trapped gas between the high melting temperature bond glass and the MCP wafer. During thermal processing, the trapped gas expanded and displaced the softened channel glass to form a spherical inclusion. This defect was eliminated by grinding the prefritted bond wafer and channel plate wafer to a flatness which ensured intimate contact prior to fusion. Elliptical blowholes or blemishes were introduced during the fiber draw stage. Contaminants trapped between the core bar and clad tubing volatized providing large quantities of expanding gas. These pockets of gas became elongated to an ellipsoidal shape during fiber draw. Special cleanliness procedures were developed for the grinding, polishing, and acid etching of core bars. Improvements in channel curvature fabrication were implemented. The design of the shearing fixture was evaluated. A new design was developed which eliminated an off-axis moment. The shearing furnace design was evaluated. Steady state thermal conditions instead of thermal transient conditions were determined to reduce curvature nonuniformity.

Laprade, Bruce N.↗
NASA NTRS2012

Fabrication of an Absorber-Coupled MKID Detector

Absorber-coupled microwave kinetic inductance detector (MKID) arrays were developed for submillimeter and far-infrared astronomy. These sensors comprise arrays of lambda/2 stepped microwave impedance resonators patterned on a 1.5-mm-thick silicon membrane, which is optimized for optical coupling. The detector elements are supported on a 380-mm-thick micro-machined silicon wafer. The resonators consist of parallel plate aluminum transmission lines coupled to low-impedance Nb microstrip traces of variable length, which set the resonant frequency of each resonator. This allows for multiplexed microwave readout and, consequently, good spatial discrimination between pixels in the array. The transmission lines simultaneously act to absorb optical power and employ an appropriate surface impedance and effective filling fraction. The fabrication techniques demonstrate high-fabrication yield of MKID arrays on large, single-crystal membranes and sub-micron front-to-back alignment of the micro strip circuit. An MKID is a detector that operates upon the principle that a superconducting material s kinetic inductance and surface resistance will change in response to being exposed to radiation with a power density sufficient to break its Cooper pairs. When integrated as part of a resonant circuit, the change in surface impedance will result in a shift in its resonance frequency and a decrease of its quality factor. In this approach, incident power creates quasiparticles inside a superconducting resonator, which is configured to match the impedance of free space in order to absorb the radiation being detected. For this reason MKIDs are attractive for use in large-format focal plane arrays, because they are easily multiplexed in the frequency domain and their fabrication is straightforward. The fabrication process can be summarized in seven steps: (1) Alignment marks are lithographically patterned and etched all the way through a silicon on insulator (SOI) wafer, which consists of a thin silicon membrane bonded to a thick silicon handle wafer. (2) The metal microwave circuitry on the front of the membrane is patterned and etched. (3) The wafer is then temporarily bonded with wafer wax to a Pyrex wafer, with the SOI side abutting the Pyrex. (4) The silicon handle component of the SOI wafer is subsequently etched away so as to expose the membrane backside. (5) The wafer is flipped over, and metal microwave circuitry is patterned and etched on the membrane backside. Furthermore, cuts in the membrane are made so as to define the individual detector array chips. (6) Silicon frames are micromachined and glued to the silicon membrane. (7) The membranes, which are now attached to the frames, are released from the Pyrex wafer via dissolution of the wafer wax in acetone.

Brown, Ari↗
NASA NTRS1980

Electrostatic bonding of thin (approximately 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (approximately 2 mil) silicon wafers and solar cells

Electrostatic bonding (ESB) of thin (3 mil) Corning 7070 cover glasses to Ta2O5 AR-coated thin (2 mil) silicon wafers and solar cells is investigated. An experimental program was conducted to establish the effects of variations in pressure, voltage, temperature, time, Ta2O5 thickness, and various prebond glass treatments. Flat wafers without contact grids were used to study the basic effects for bonding to semiconductor surfaces typical of solar cells. Solar cells with three different grid patterns were used to determine additional requirements caused by the raised metallic contacts.

Egelkrout, D. W.↗
NASA NTRS1992

Sub-Kelvin resistance thermometer

A device capable of accurate temperature measurement down to 0.01 K of a particular object is discussed. The device is comprised of the following: a heat sink wafer; a first conducting pad bonded near one end of the heat sink wafer; a second conducting pad bonded near the other end of the heat sink wafer; and an oblong doped semiconductor crystal such as germanium. The oblong doped semiconductor crystal has a third conducting pad bonded on its bottom surface with the oblong doped semiconductor crystal bonded to the heat sink wafer by having the fourth conducting pad bonded to the first conducting pad. A wire is bonded between the second and third conducting pads. Current and voltage wires bonded to the first and second conducting pads measure the change in resistance of the oblong doped semiconductor crystal; this indicates the temperature of the object whose temperature is to be measured.

Castles, Stephen H.↗
NASA NTRS1981

Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

Egelkrout, D. W.↗
DOE OSTI2021

Method of fabricating photosensitive devices with reduced process-temperature budget

A method is provided for fabricating a backside-illuminated photodetector in which a device wafer is joined to a readout wafer in an IC hybridization step. Before the IC hybridization step, the device layer is defined in the device wafer, and an LPCVD layer is formed over the device layer. The LPCVD layer may be a passivation layer, an antireflection coating, or both. The side of the device wafer having the LPCVD layer is bonded to a handle wafer, the IC is hybridized by mating the device wafer to the readout wafer, and the handle wafer is then removed, exposing the LPCVD layer. Because the LPCVD layer is formed before the active devices are fabricated, it can be made by high-temperature techniques for deposition and processing. Accordingly, a layer of high quality can be fabricated without any hazard to the active devices.

Kay, Randolph R.↗
NASA NTRS2009

Alternative Packaging for Back-Illuminated Imagers

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Pain, Bedabrata↗
NASA NTRS2003

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Yang, Eui-Hyeok↗
DOE OSTI2022

Fine Pitch Bonding for High Density Interconnects

CTE (coefficient of thermal expansion) mismatch between two wafers has potential for brittle failure when large areas are bonded on top of one another (wafer to wafer or wafer to die bonds). To address this type of failure, we proposed patterning a polymer around metallic interconnects. For this project, utilized benzo cyclobutene (BCB) to form the bond and accommodate stress. For the metal interconnects, we used indium. To determine the benefits of utilizing BCB, mechanical shear testing of die bonding with just BCB were compared to die bonded just with oxide. These tests demonstrated that BCB, when cured for only 30 minutes and bonded at 200°C, the BCB was able to withstand shear forces similar to oxide. Furthermore, when the BCB did fail, it experienced a more ductile failure, allowing the silicon to crack, rather than shatter. To demonstrate the feasibility of using BCB between indium interconnects, wafers were pattered with layers of BCB with vias for indium or ENEPIG (electroless nickel, electroless palladium, immersion gold). Subsequently, these wafers were pattered with a variety of indium or ENEPIG interconnect pitches, diameters, and heights. These dies were bonded under a variety of conditions, and those that held a bond, were cross-sectioned and imaged. Images revealed that certain bonding conditions allow for interconnects and BCB to achieve a void-less bond and thus demonstrate that utilizing polymers in place of oxide is a feasible way to reduce CTE stress.

36 MATERIALS SCIENCE↗
NASA NTRS1995

Initial results for the silicon monolithically interconnected solar cell product

This proprietary technology is based on AstroPower's electrostatic bonding and innovative silicon solar cell processing techniques. Electrostatic bonding allows silicon wafers to be permanently attached to a thermally matched glass superstrate and then thinned to final thicknesses less than 25 micron. These devices are based on the features of a thin, light-trapping silicon solar cell: high voltage, high current, light weight (high specific power) and high radiation resistance. Monolithic interconnection allows the fabrication costs on a per watt basis to be roughly independent of the array size, power or voltage, therefore, the cost effectiveness to manufacture solar cell arrays with output powers ranging from milliwatts up to four watts and output voltages ranging from 5 to 500 volts will be similar. This compares favorably to conventionally manufactured, commercial solar cell arrays, where handling of small parts is very labor intensive and costly. In this way, a wide variety of product specifications can be met using the same fabrication techniques. Prototype solar cells have demonstrated efficiencies greater than 11%. An open-circuit voltage of 5.4 volts, fill factor of 65%, and short-circuit current density of 28 mA/sq cm at AM1.5 illumination are typical. Future efforts are being directed to optimization of the solar cell operating characteristics as well as production processing. The monolithic approach has a number of inherent advantages, including reduced cost per interconnect and increased reliability of array connections. These features make this proprietary technology an excellent candidate for a large number of consumer products.

Dinetta, L. C.↗