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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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58 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Understanding the origin of Tabula Rasa-induced defects in n-type Cz c-Si: The case of nitrogen atmosphere

Phosphorus-doped Czochralski-grown silicon (Cz-Si) has been gaining market share in the large-scale manufacturing of high-efficiency silicon (Si)-based photovoltaic (PV) devices thanks to higher carrier lifetimes than their boron-doped counterpart. However, the fabrication of n-type Cz-Si based solar cells often requires process steps with much higher temperatures and longer times than p-type Silicon. Defect interaction with the high temperatures during such processes tend to be detrimental to the n-type Cz-Si carrier lifetime, therefore limiting the final device efficiency. Short thermal anneals before cell processing, known as Tabula Rasa (TR), have been proposed to mitigate the thermally induced lifetime degradation during n-type Cz-Si solar cell fabrication. This work thoroughly investigates the defects responsible for the lifetime degradation after TR in a N 2 atmosphere treatment. We use temperature-injection-dependent lifetime spectroscopy and the thickness variation method to decouple the effects of TR treatment in the bulk and the surface of the n-type Cz-Si wafers. Using the defect parameter contour mapping (DPCM), we identify the defect energy level (E t ) and the capture cross-section ratio (k) of the most likely process-induced defect, which aligns with previously proposed Si vacancy-associated defects. The DPCM reveals that these vacancy-associated defects have a shallow energy level E t - E v ~0.13 eV and very efficient electron capture cross section k~600. Unexpectedly, the bulk degradation due to vacancy defects in the volume of the wafer, is accompanied by a significant increase in the surface recombination as well. Through evaluating the surface recombination velocity temperature- and injection dependence, we show that after TR, at room temperature and for an injection level of 10 15 cm -3 , in a wafer passivated with a-Si:H(i) the surface recombination dominates the overall lifetime response. Here we hypothesize that the near surface vacancy-associated bulk defects play a role in lowering the electron diffusion current into the a-Si:H(i) from the c-Si(n) reducing the field-effect passivation.

14 SOLAR ENERGY↗
DOE OSTI2020

Reflectance of Silicon Photomultipliers at Vacuum Ultraviolet Wavelengths

Characterization of the vacuum ultraviolet (VUV) reflectance of silicon photomultipliers (SiPMs) is important for large-scale SiPM-based photodetector systems. In this work, we report the angular dependence of the specular reflectance in vacuum of SiPMs manufactured by Fondazionc Bruno Kessler (FBK) and Hamamatsu Photonics K.K. (HPK) over wavelengths ranging from 120 to 280 nm. Refractive index and extinction coefficient of the thin silicon-dioxide film deposited on the surface of the FBK SiPMs are derived from reflectance data of an FBK silicon wafer with the same deposited oxide film as SiPMs. The diffuse reflectance of SiPMs is also measured at 193 nm. We use the VUV spectral dependence of the optical constants to predict the reflectance of the FBK silicon wafer and FBK SiPMs in liquid xenon.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2024

In-flight performance of S PIDER'S 280-GHz receivers

S PIDER is a balloon-borne instrument designed to map the cosmic microwave background at degree-angular scales in the presence of Galactic foregrounds. S PIDER has mapped a large sky area in the Southern Hemisphere using more than 2000 transition-edge sensors (TESs) during two NASA Long Duration Balloon flights above the Antarctic continent. During its first flight in January 2015, S PIDER observed in the 95 GHz and 150 GHz frequency bands, setting constraints on the B-mode signature of primordial gravitational waves. Its second flight in the 2022-23 season added new receivers at 280 GHz, each using an array of TESs coupled to the sky through feedhorns formed from stacks of silicon wafers. Here, these receivers are optimized to produce deep maps of polarized Galactic dust emission over a large sky area, providing a unique data set with lasting value to the field. In this work, we describe the instrument’s performance during S PIDER'S second flight.

280 GHz cosmology↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗