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At least 721 records · Page 40

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NASA NTRS2015

Periodic Cellular Structure Technology for Shape Memory Alloys

Shape memory alloys are being considered for a wide variety of adaptive components for engine and airframe applications because they can undergo large amounts of strain and then revert to their original shape upon heating or unloading. Transition45 Technologies, Inc., has developed an innovative periodic cellular structure (PCS) technology for shape memory alloys that enables fabrication of complex bulk configurations, such as lattice block structures. These innovative structures are manufactured using an advanced reactive metal casting technology that offers a relatively low cost and established approach for constructing near-net shape aerospace components. Transition45 is continuing to characterize these structures to determine how best to design a PCS to better exploit the use of shape memory alloys in aerospace applications.

Chen, Edward Y.↗

NASA NTRS2016

Thermomechanical Methodology for Stabilizing Shape Memory Alloy (SMA) Response

Methods and apparatuses for stabilizing the strain-temperature response for a shape memory alloy are provided. To perform stabilization of a second sample of the shape memory alloy, a first sample of the shape memory alloy is selected for isobaric treatment and the second sample is selected for isothermal treatment. When applying the isobaric treatment to the first sample, a constant stress is applied to the first sample. Temperature is also cycled from a minimum temperature to a maximum temperature until a strain on the first sample stabilizes. Once the strain on the first sample stabilizes, the isothermal treatment is performed on the second sample. During isothermal treatment, different levels of stress on the second sample are applied until a strain on the second sample matches the stabilized strain on the first sample.

Padula, Santo A., II↗

NASA NTRS2010

Memory Overview - Technologies and Needs

As NASA has evolved it's usage of spaceflight computing, memory applications have followed as well. In this talk, we will discuss the history of NASA's memories from magnetic core and tape recorders to current semiconductor approaches. We will briefly describe current functional memory usage in NASA space systems followed by a description of potential radiation-induced failure modes along with considerations for reliable system design.

LaBel, Kenneth A.↗

NASA NTRS2018

Polyurethane Microparticles for Stimuli Response and Reduced Oxidative Degradation in Highly Porous Shape Memory Polymers

Shape memory polymers (SMPs) have been found to be promising biomaterials for a variety of medical applications; however, the clinical translation of such technology is dependent on tailorable properties such as gravimetric changes in degradation environments. For SMPs synthesized from amino-alcohols, oxidation resulting in rapid mass loss may be problematic in terms of loss of material functionality as well as toxicity and cytocompatibility concerns. Control of gravimetric changes was achieved through the incorporation of small molecule antioxidants, either directly into the polymer matrix or included in microparticles to form a SMP composite material. Direct incorporation of small molecule antioxidants, such as phenolic alcohols, was found to alter shape memory attributes and increase elastic modulus at the expense of the strain to failure. Such changes could not ensure retention of the antioxidants and therefore did not increase oxidative stability. However, the inclusion of antioxidants in microparticles was found to produce materials with similar thermomechanical and shape memory properties while increasing oxidative resistance compared to controls. The microparticle composite SMPs also act as a platform for environmental sensing, such as pH-dependent fluorescence shifts and payload release, as demonstrated by fluorescent dyes and the release of antioxidants. The use of polyurethane-urea microparticles in porous SMPs is demonstrated to increase biostability of the materials, by approximately 25%, and ultimately extend their lifespan for use in aneurysm occlusion as determined through calculated in vivo degradation rates corresponding to a porcine aneurysm environment.

Weems, A. C.↗

NASA NTRS2016

Total Ionizing Dose Response of SDRAM, DDR2 and DDR3 Memories

Total Ionizing Dose response (ID) of SDRAM (Synchronous Dynamic Random Access Memory), DDR2 (Double Data Rate2) and DDR3 (Double Data Rate3) memories is reported in static bias, and auto refresh modes. Data analysis reveals some types of memory have significant increases in stuck bits during TID exposure when refreshed.

Amrbar, Mehran↗

NASA NTRS2001

A radiation - tolerant, low - power non - volatile memory based on silicon nanocrystal quantum dots.

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in Si02 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled.

Green, M. L.↗

NASA NTRS2012

Radiation tests of highly scaled, high-density, commercial, nonvolatile NAND flash memories— update 2012

The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

Allen, Gregory R.↗

NASA NTRS2021

Meta-aerogels: Auxetic Shape-memory Polyurethane Aerogels

Shape-memory poly(isocyanurate-urethane) (PIR-PUR) aerogels are low-density monolithic nanoporous solids that remember and return to their permanent shape through a heating actuation step. Herein, through structural design at the macro scale, the shape-memory response is augmented with an auxetic effect manifested by a negative Poisson’s ratio of approximately -0.8 at 15% compressive strain. Thus, auxetic shape-memory PIR-PUR monoliths experience volume contraction upon compression at a temperature above the glass transition temperature of the base polymer (Tg ~ 30 °C), and they can be stowed indefinitely in that temporary shape by cooling below Tg. By heating back above Tg, the compressed/shrunk form expands back to their original shape/size. This technology is relevant to a broad range of industries spanning the commercial, aeronautical, and aerospace sectors. The materials are referred to as meta-aerogels and their potential applications include minimally invasive medical devices, soft robotics, and in situations where volume is at a premium, as for example for storage of deployable space structures and planetary habitats during transport to the point of service.

Sadeq Malakooti↗

DOE OSTI2017

Memory Compression Techniques for Network Address Management in MPI

MPI allows applications to treat processes as a logical collection of integer ranks for each MPI communicator, while internally translating these logical ranks into actual network addresses. In current MPI implementations the management and lookup of such network addresses use memory sizes that are proportional to the number of processes in each communicator. In this paper, we propose a new mechanism, called AV-Rankmap, for managing such translation. AV-Rankmap takes advantage of logical patterns in rank-address mapping that most applications naturally tend to have, and it exploits the fact that some parts of network address structures are naturally more performance critical than others. It uses this information to compress the memory used for network address management. We demonstrate that AV-Rankmap can achieve performance similar to or better than that of other MPI implementations while using significantly less memory.

Guo, Yanfei↗

DOE OSTI2017

Resistively heated shape memory polymer device

A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.

Marion, III, John E.↗

DOE OSTI2017

Performance Study of the First 2D Prototype of Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Extremely fast pattern recognition capabilities are necessary to find and fit billions of tracks at the hardware trigger level produced every second anticipated at high luminosity LHC (HL-LHC) running conditions. Associative Memory (AM) based approaches for fast pattern recognition have been proposed as a potential solution to the tracking trigger. However, at the HL-LHC, there is much less time available and speed performance must be improved over previous systems while maintaining a comparable number of patterns. The Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project aims to achieve the target pattern density and performance goal using 3DIC technology. The first step taken in the VIPRAM work was the development of a 2D prototype (protoVIPRAM00) in which the associative memory building blocks were designed to be compatible with the 3D integration. In this paper, we present the results from extensive performance studies of the protoVIPRAM00 chip in both realistic HL-LHC and extreme conditions. Results indicate that the chip operates at the design frequency of 100 MHz with perfect correctness in realistic conditions and conclude that the building blocks are ready for 3D stacking. We also present performance boundary characterization of the chip under extreme conditions.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2018

Device and methods for writing and erasing analog information in small memory units via voltage pulses

Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.

42 ENGINEERING↗

DOE OSTI2018

Efficient accesses of data structures using processing near memory

Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2019

Encoding data within a crossbar memory array

In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.

Muralimanohar, Naveen↗

DOE OSTI2017

Resistively heated shape memory polymer device

Marion, III, John E.↗

DOE OSTI2019

Hot page selection in multi-level memory hierarchies

Systems, apparatuses, and methods for sorting memory pages in a multi-level heterogeneous memory architecture. The system may classify pages into a first “hot” category or a second “cold” category. The system may attempt to place the “hot” pages into the memory level(s) closest to the systems' processor cores. The system may track parameters associated with each page, with the parameters including number of accesses, types of accesses, power consumed per access, temperature, wearability, and/or other parameters. Based on these parameters, the system may generate a score for each page. Then, the system may compare the score of each page to a threshold. If the score of a given page is greater than the threshold, the given page may be designated as “hot”. If the score of the given page is less than the threshold, the given page may be designated as “cold”.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2019

Method and apparatus for performing memory prefetching

A method and apparatus for performing memory prefetching includes determining whether to initiate prefetching. Upon a determination to initiate prefetching, a first memory row is determined as a suitable prefetch candidate, and it is determined whether a particular set of one or more cachelines of the first memory row is to be prefetched.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2019

Writing of a magnetic memory with electric pulses

Methods and memory circuits for altering a magnetic direction of a magnetic memory cell using picosecond electric current pulses are disclosed. One method includes directing a first electric current pulse through the magnetic memory cell that includes a ferrimagnetic material layer to heat the ferrimagnetic material layer to toggle a magnetic direction of the ferrimagnetic material layer from a first magnetic direction to a second magnetic direction.

Yang, Yang↗