SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
MSR-Genie is a vendor-neutral tool for fast and efficient queries about model-specific registers (MSRs). The tool allows end users to query bi-directionally across MSR lists as well as processor families and models, and provides them with guidance on appropriate bitmasks. The msr-genie tool is open-source and easily extensible, and currently supports 30 Intel processor models and two-thousand unique MSRs.
In the area of power electronics control, Field Programmable Gate Arrays (FPGAs) have the capability to outperform their Digital Signal Processor (DSP) counterparts due to the FPGA’s ability to implement true parallel processing and therefore facilitate higher switching frequencies, higher control bandwidth, and/or enhanced functionality. National Instruments (NI) has developed two platforms, Compact RIO (cRIO) and Single Board RIO (sbRIO), which combine a real-time processor with an FPGA. The FPGA can be programmed with a subset of the well-known LabVIEW graphical programming language. The candidate software implements complete control algorithms in LabVIEW FPGA for a DC Transformer (DCX) based on a dual active bridge (DAB). A DCX is an isolated bi-directional DC-DC converter designed to operate at unity conversion ratio, M, defined by where Vin is the primary-side DC bus voltage, Vout is the secondary-side DC bus voltage, and n is the turns ratio of the embedded high frequency transformer (HFX). The DCX based on a DAB incorporates two H-bridges, a resonant inductor, and an HFX to provide this functionality. The candidate software employs phase-shift modulation of the two H-bridges and a feedback loop to regulate the conversion ratio at unity. The software also includes alarm-handling capabilities as well as debugging and tuning tools. The software fits on the Xilinx Virtex V LX110 FPGA embedded in the NI cRIO-9118 FPGA chassis, and with a 40 MHz base clock, supports a modulation update rate of 40 MHz, and user-settable switching frequencies and synchronized control loop update rates of tens of kHz.
In the area of power electronics control, Field Programmable Gate Arrays (FPGAs) have the capability to outperform their Digital Signal Processor (DSP) counterparts due to the FPGA’s ability to implement true parallel processing and therefore facilitate higher switching frequencies, higher control bandwidth, and/or enhanced functionality. National Instruments (NI) has developed two platforms, Compact RIO (cRIO) and Single Board RIO (sbRIO), which combine a real-time processor with an FPGA. The FPGA can be programmed with a subset of the well-known LabVIEW graphical programming language. The use of cRIO and sbRIO for power electronics control has developed over the last few years to include control of three-phase inverters. Most three-phase inverter topologies include three switching legs. The addition of a fourth-leg to natively generate the neutral connection allows the inverter to serve single-phase loads in a microgrid or stand-alone power system and to balance the three-phase voltages in the presence of significant load imbalance. However, the control of a four-leg inverter is much more complex. In particular, instead of standard two-dimensional space vector modulation (SVM), the inverter requires three-dimensional space vector modulation (3D-SVM). The candidate software implements complete control algorithms in LabVIEW FPGA for a three-phase four-leg inverter. The software includes feedback control loops, three-dimensional space vector modulation gate-drive algorithms, advanced alarm handling capabilities, contactor control, power measurements, and debugging and tuning tools. The feedback control loops allow inverter operation in AC voltage control, AC current control, or DC bus voltage control modes based on external mode selection by a user or supervisory controller. The software includes the ability to synchronize its AC output to the grid or other voltage-source before connection. The software also includes provisions to allow inverter operation in parallel with other voltage regulating devices on the AC or DC buses. This flexibility allows the Inverter to operate as a stand-alone voltage source, connected to the grid, or in parallel with other controllable voltage sources as part of a microgrid or remote power system. In addition, as the inverter is expected to operate under severe unbalanced conditions, the software includes algorithms to accurately compute real and reactive power for each phase based on definitions provided in the IEEE Standard 1459: IEEE Standard Definitions for the Measurement of Electric Power Quantities Under Sinusoidal, Nonsinusoidal, Balanced, or Unbalanced Conditions. Finally, the software includes code to output analog signals for debugging and for tuning of control loops. The software fits on the Xilinx Virtex V LX110 FPGA embedded in the NI cRIO-9118 FPGA chassis, and with a 40 MHz base clock, supports a modulation update rate of 40 MHz, user-settable switching frequencies and synchronized control loop update rates of tens of kHz, and reference waveform generation, including Phase Lock Loop (PLL), update rate of 100 kHz.
The proposed system is written in the hardware description language (HDL) verilog targeting an FPGA board. It is intended as a testbed to explore architecture tradeoffs in multi-tiled heterogeneous architectures. Although we target FPGAs, the system can be implemented as a monolithic SoC or a package comprised of many chiplets that are interconnected in the same package using a NoC. The proposed NoC is lightweight and follows an axi-lite interface. The endpoints of the NoC are a heterogeneous mix of "tiles" as endpoints that are general purpose processors, fixed function accelerators, and programmable accelerators. We assume that the network interfaces for the NoC endpoints are all addressable in a global name-space in that they represent an address range (for memory addresses) or a range of unique identifiers that are associated with each individual tile. This makes the functionality abstract from the standpoint of the NoC design details. Message queues offer a direct inter-processor interface between peer general purpose cores and diverse accelerators that comprise an SoC. Although they share the same NoC infrastructure for inter-tile communication within an SoC or SiP, the hardware message queues bypass the memory hierarchy and thus do not pollute the memory state or invoke the cache coherence mechanism.
NWQSim is a quantum circuit simulation environment developed at PNNL. It currently includes two major components: a state-vector simulator (SV-Sim) and a density matrix simulator (DM-Sim) and we may add more components, such as a Clifford simulator, in the future effort. NWQSim has two language interface: C/C++ and Python. It supports Q#/QDK frontend through QIR and QIR-runtime. It supports Qiskit and Cirq frontends through OpenQASM. NWQSim runs on several backends: Intel-CPU, Intel-Xeon-Phi, AMD-CPU, AMD-GPU, NVIDIA-GPU, and IBM-CPU. It supports three modes: (1) single processor, such as a single CPU (with and without AVX2 and AVX512 acceleration), a single NVIDIA GPU or a single AMD GPU; (2) single-node-multi-processors, such as multi-CPUs/Xeon-Phis, multi-NVIDA/AMD GPUs; (3) multi-nodes, such as a CPU cluster, a Xeon-Phi cluster (e.g., ANL Theta, NERSC Cori), an NVIDIA cluster (e.g., ORNL Summit, NERSC Perlmutter).
STOMPX is an OpenMPI implementation of selected operational modes of the Subsurface Transport Over Multiple Phases numerical simulator. STOMPX is designed to execute with both shared- and distributed-memory computer architectures. This implementation of the simulator is designed to solve the same problems as the STOMP simulator, but taking advantage of multiple processor execution through the OpenMPI language and libraries. The STOMP simulator is written in Fortran 90 and operates on single processors or shared-memory computer architectures. The STOMPX simulator extends execution to distributed-memory computer architectures, including super computers
DISTRI is an advanced network simulator designed for multi-facility computational infrastructures with agentic behavior. It simulates HPC facilities where computational resources act as autonomous agents, making intelligent decisions about job scheduling, load balancing, and resource allocation. The simulator focuses on developing and testing decentralized algorithms that promote resilience and efficiency in multi-facility environments. Key Features: - Agentic Resource Behavior: Processors and DTNs act as autonomous agents with decision-making capabilities - Pheromone-Based Load Balancing: Decentralized load balancing inspired by ant colony optimization - Dual Topology Support: Mesh (normal operations) and Dumbell (network testing) topologies - Comprehensive TCP Simulation: Realistic TCP implementations with multiple congestion control algorithms - Failure Resilience Testing: Processor failure simulation with automatic job reassignment - Extensive Visualization: Detailed performance analysis and metrics collection - Research-Ready: Designed for algorithm development and benchmarking
Power is an often-cited reason for the move to advanced architectures on the path to Exascale computing. Here, this is due to practical considerations related to delivering enough power to successfully site and operate these machines, as well as concerns about energy usage while running large simulations. Since obtaining accurate power measurements can be challenging, it may be tempting to use the processor thermal design power (TDP) as a surrogate due to its simplicity and availability. However, TDP is not indicative of typical power usage while running simulations. Using commodity and advanced technology systems at Lawrence Livermore and Sandia National Labs, we performed a series of experiments to measure power and energy usage in running simulation codes. These experiments indicate that large scale Lawrence Livermore simulation codes are significantly more efficient than a simple processor TDP model might suggest.
Sequence alignment algorithms are a key component of many bioinformatics applications. Though various fast Smith-Waterman local sequence alignment implementations have been developed for x86 CPUs, most are embedded into larger database search tools. In addition, fast implementations of Needleman-Wunsch global sequence alignment and its semi-global variants are not as widespread. This article presents the first software library for local, global, and semi-global pairwise intra-sequence alignments and improves the performance of previous intra-sequence implementations. As a result, a faster intra-sequence pairwise alignment implementation is described and benchmarked. Using a 375 residue query sequence a speed of 136 billion cell updates per second (GCUPS) was achieved on a dual Intel Xeon E5-2670 12-core processor system, the highest reported for an implementation based on Farrar’s ’striped’ approach. When using only a single thread, parasail was 1.7 times faster than Rognes’s SWIPE. For many score matrices, parasail is faster than BLAST. The software library is designed for 64 bit Linux, OS X, or Windows on processors with SSE2, SSE41, or AVX2. Source code is available from https://github.com/jeffdaily/parasail under the Battelle BSD-style license. In conclusion, applications that require optimal alignment scores could benefit from the improved performance. For the first time, SIMD global, semi-global, and local alignments are available in a stand-alone C library.
Abstract Quantum search algorithm (also known as Grover's algorithm) lays the foundation for many other quantum algorithms. Although it is very simple, its implementation is limited on noisy intermediate-scale quantum (NISQ) processors. Grover's algorithm was designed without considering the physical resources, such as depth, in the real implementations. Therefore, Grover's algorithm can be improved for NISQ devices. In this paper, we demonstrate how to implement quantum search algorithms better on NISQ devices. We present detailed benchmarks of the five-qubit quantum search algorithm on different quantum processors, including IBMQ, IonQ, and Honeywell quantum devices. We report the highest success probability of the five-qubit search algorithm compared to previous works. Our results show that designing the error-aware quantum search algorithms is possible, which can maximally harness the power of NISQ computers.
Comprehensive analysis of high-performance computing (HPC) systems requires linking workload execution to system behavior. This kind of analysis is vital for diagnosing performance issues, managing capacity, detecting anomalous workloads, and understanding how applications interact with system hardware. This job-centric telemetry dataset unifies scheduler job records with node-level measurements, enabling direct association between workloads and their corresponding power, thermal, and performance characteristics. It contains sanitized, scheduler related metadata for 152,400 individual jobs that ran on the Frontier supercomputer and ended on selected days throughout 2024 and 2025, a subpopulation of ~6.8% of the total number of allocated jobs with non-zero run time on the system over that same period. Each is linked with files that contain telemetry time series records of the power utilization and temperature behavior of its allocated nodes and their processors during the run time of the job. Where available, a portion of the job files also contain network performance time series. Jobs are sampled from select days that reflect normal levels of user activity and possess job size distributions with large numbers of leadership class jobs (>20% of Frontier nodes). Jobs in this dataset attempt to best represent successful user workflows.
From nuclear materials accountability to homeland security, the need for improved nuclear material detection, assay, and authentication has grown over the past decades. Starting in the 1940s, neutron multiplicity counting techniques have enabled quantitative evaluation of masses and multiplications of fissile materials. In this paper, we propose a new method to compute uncertainties on these parameters using a model-based sequential Bayesian processor, resulting in credible regions in the fissile material mass and multiplication space. These uncertainties will enable us to evaluate quantitatively proposed improvements to the theoretical fission chain model. Additionally, because the processor can calculate uncertainties in real time, it is a useful tool in applications such as portal monitoring: monitoring can stop as soon as a preset confidence of non-threat is reached.
The ability of spatial light modulators (SLMs) to modify the amplitude and phase of light has proved them invaluable to the optics and photonics community. In many applications, the bit-depth of SLMs is a major limiting factor dictated by a digital processor. As a result, there is usually a compromise between refresh speed and bit-depth. Here, we present a method to increase the effective bit-depth of SLMs, which utilizes a linear slope, as is commonly applied to deal with the zeroth-order effect. This technique was tested using two interferometric transient absorption spectroscopy setups. Through the high harmonic generation in gases producing a train of attosecond pulses and harmonics from solids in the ultraviolet, two pulses are generated that interfere in the far field providing a measurement of the optical phase. An increase in the precision far beyond the limit dictated by the digital processor in the bit-depth was found.
Information barriers are trusted measurement systems to confirm the authenticity of nuclear warheads based on their radiation signatures. Traditional inspection systems rely on complex electronics both for data acquisition and processing. Several research efforts have produced prototype systems, but it has proven difficult to demonstrate that hidden switches and side channels do not exist. After almost thirty years of research and development, no viable and widely accepted system has emerged. We pursue a fundamentally different approach: Our prototype of an inspection system uses vintage hardware built around a 6502 processor. The processor uses 8-micron technology and has only about 4,200 transistors. Vintage electronics may have a number of important advantages for applications where two parties need to simultaneously establish trust in the hardware used. CPUs designed in the distant past, at a time when their use for sensitive measurements was never envisioned, drastically reduce concerns that the other party implemented backdoors or hidden switches on the hardware level. We demonstrate the performance of a prototype system using an Apple IIe and a custom-made open-source data-processing board connected to a standard sodiumiodide radiation detector for low-resolution gamma spectroscopy. Data processing and analysis is exclusively done on the Apple IIe hardware. We show that subtle differences in radiation signatures can be detected in 2–3 minutes based on the result of a simple chi-squared test. Vintage electronics may therefore offer a new path toward fieldable, trusted information barriers.
Cloud data centers are projected to be the fastest growing segment of the server market through 2015, according to IDC. Increasingly people and businesses rely on the Cloud to deliver digital content quickly and efficiently. Recovery Act funding from the Department of Energy has helped SeaMicro's technologies enhance the total cost of operation, performance and energy efficiency in large data center and Cloud environments. SeaMicro's innovative supercomputer fabric connects thousands of processor cores, memory, storage and input/output traffic. The company's fabric supports multiple processor instruction sets. Current systems featuring SeaMicro technology typically use one quarter the power and take one sixth the space of traditional servers with the same compute performance, yet deliver up to 12 times the bandwidth per core. Mozilla and eHarmony are two customers successfully using SeaMicro's technology. Numerous non-public customers have been successfully using the SeaMicro product in test and production facilities. As a result of the Recovery Act funding from the U.S. Department of Energy, more than 50 direct jobs were created at SeaMicro. To date, they primarily have been high-value, engineering jobs. Hardware, software and manufacturing engineering positions have been created, as well as sales and sales engineering. The positions have allowed SeaMicro to significantly accelerate engineering development and accelerate commercialization. As a result, commercialization and delivery to market are months ahead of initial schedule. Additional jobs were indirectly created through the development of the SeaMicro product. Through many years of research and hard work prior to receipt of public funding, SeaMicro was awarded 2 patents for its work. SeaMicro's product led the way for industry leaders to reconsider the market for low power servers and create new product lines. With valuable support of the U.S. Department of Energy and through SeaMicro's product, the market has been reshaped by the company's unique approach and ground breaking technology.
The UNAP DCM board is capable of measuring currents with a dynamic range of 3 x 10 -14 A to 3 x 10 -4 A. The design of the DCM closely matches the proven N-1 minigrand family DCM design. The most significant difference is the replacement of the Actel FPGA with an SPI I/O expander. The original DCM design used an Actel FPGA to communicate with the processor over the expansion bus controling the DCM gain and filtering. The UNAP processor communicates with the UDA FPGA over the cPCI bus. The UNAP DCM control functions are accomplished in the UDA FPGA and communicated to the DCM board via an SPI bus.
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: ■ Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). Note that this includes support for most popular parallel and serial computers. ■ Improved performance for all numerical kernels (e.g., time integrator, nonlinear and linear solvers) through state-of-the-art algorithms and novel techniques. ■ Device models which are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). ■ Object-oriented code design and implementation using modern coding practices that ensure that the Xyce Parallel Electronic Simulator will be maintainable and extensible far into the future. Xyce is a parallel code in the most general sense of the phrase - a message passing parallel implementation - which allows it to run efficiently on the widest possible number of computing platforms. These include serial, shared-memory and distributed-memory parallel as well as heterogeneous platforms. Careful attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows. The development of Xyce provides a platform for computational research and development aimed specifically at the needs of the Laboratory. With Xyce, Sandia has an “in-house” capability with which both new electrical (e.g., device model development) and algorithmic (e.g., faster time-integration methods, parallel solver algorithms) research and development can be performed. As a result, Xyce is a unique electrical simulation capability, designed to meet the unique needs of the laboratory
The Multi-Instrument Collect, MIC, program is designed for unattended collection and saving of data from multiple, distributed data acquisition instruments. It is highly configurable, supporting collection of data from up to 128 instruments on up to 128 communications channels. MIC also provides the ability to copy data to removable disks for exporting the data it collects. MIC is a complex state-of-the-art multi-tasking application. It is designed to function on a fast multi-processor system but can run adequately on a single-processor platform.