SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.
A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.
A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.
The Stirling Generator Testbed is an on-going effort to demonstrate performance, behaviors, and typical interfaces that would be present in a flight-like Stirling radioisotope power system. Design of the Testbed occurred over the past several years, with the acquisition of parts beginning in 2022. The assembly, integration and initial test campaign for the Testbed involved an array of steps and processes, culminating with the initial test results.
A comprehensive framework was explored and validated for rapid deployment and testing of custom flight control logic using the Inexpensive Multirotor Platform for Advanced Controls Testing (IMPACT). This vehicle facilitated the efficient validation and refinement of a custom flight control algorithm, which was designed using Simulink and deployed onto a Pixhawk flight computer running PX4 firmware through the utilization of the MathWorks UAV Toolbox. The robust and cost-effective design of IMPACT provides the groundwork for future flight testing of flight controls and model development research for electric vertical takeoff and landing (eVTOL) aircraft.
The test program conducted to characterize the steady state stability, thermal, and performance characteristics of the integrated thrust chamber assembly, as well as limited tests to investigate transient characteristics are described.
Ground vibration testing has been an integral tool for developing new launch vehicles throughout the space age. Several launch vehicles have been lost due to problems that would have been detected by early vibration testing, including Ariane 5, Delta III, and Falcon 1. NASA will leverage experience and testing hardware developed during the Saturn and Shuttle programs to perform ground vibration testing (GVT) on the Ares I crew launch vehicle and Ares V cargo launch vehicle stacks. NASA performed dynamic vehicle testing (DVT) for Saturn and mated vehicle ground vibration testing (MVGVT) for Shuttle at the Dynamic Test Stand (Test Stand 4550) at Marshall Space Flight Center (MSFC) in Huntsville, Alabama, and is now modifying that facility to support Ares I integrated vehicle ground vibration testing (IVGVT) beginning in 2012. The Ares IVGVT schedule shows most of its work being completed between 2010 and 2014. Integrated 2nd Stage Ares IVGVT will begin in 2012 and IVGVT of the entire Ares launch stack will begin in 2013. The IVGVT data is needed for the human-rated Orion launch vehicle's Design Certification Review (DCR) in early 2015. During the Apollo program, GVT detected several serious design concerns, which NASA was able to address before Saturn V flew, eliminating costly failures and potential losses of mission or crew. During the late 1970s, Test Stand 4550 was modified to support the four-body structure of the Space Shuttle. Vibration testing confirmed that the vehicle's mode shapes and frequencies were better than analytical models suggested, however, the testing also identified challenges with the rate gyro assemblies, which could have created flight instability and possibly resulted in loss of the vehicle. Today, NASA has begun modifying Test Stand 4550 to accommodate Ares I, including removing platforms needed for Shuttle testing and upgrading the dynamic test facilities to characterize the mode shapes and resonant frequencies of the vehicle. The IVGVT team expects to collect important information about the new launch vehicles, greatly increasing astronaut safety as NASA prepares to explore the Moon and beyond.
Software and hardware requirements for implementing hardware self tests are presented in support of the development of training and procedures development simulators for the space shuttle program. Self test techniques for simulation hardware and the validation of simulation performance are stipulated. The requirements of an integrated simulator self system are analyzed. Readiness tests, fault isolation tests, and incipient fault detection tests are covered.
NASA is the mission lead for the James Webb Space Telescope (JWST), the next of the "Great Observatories", scheduled for launch in 2014. It is directly responsible for the integration and test of the Integrated Science Instrument Module (ISIM), which includes a composite truss structure provided by NASA, and four science instruments sponsored and provided by NASA, the European Space Agency (ESA), the Canadian Space Agency (CSA), and the European Consortium (EC). Three of the four instruments are passively cooled and designed to operate at temperatures in the 36K to 40K range, and the fourth instrument is actively cooled to approximately 6K. The ISIM will undergo several performance tests at various levels of integration in the NASA Goddard Space Flight Center's (GSFC) Space Environment Simulator (SES), GSFC's largest thermal vacuum chamber. These activities range from Cryo-cycling the bare flight composite structure to thermal balance and performance testing of the full ISIM module. This paper describes the enhancements made to the SES chamber in order to support all cryogenic thermal vacuum testing of the ISIM. Upgrades discussed include: design and fabrication of a very large, removable and reconfigurable helium shroud; a new valve box permitting independent flow control of gaseous helium (GHe) to up to ten zones; and development of in-situ 3-dimensional photogrammetry capability in a cryogenic environment. Also presented will be select results from several facility tests already conducted to verify the chamber capabilities and optimize operational procedures, including the Helium Shroud -03 Configuration Acceptance Test, and the Helium Shroud -01 Configuration Chamber Certification Test.
Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).
Since 2016, JAXA and NASA have partnered to investigate the safe and efficient integration of unmanned aircraft systems (UAS) in disaster response operations. Through the collaboration, supporting systems from the respective agencies have been successfully integrated and demonstrated in multiple activities ranging from localized simulations and flight tests to large-scale national disaster drills. This paper describes findings from the most recent flight test by JAXA using a crewed helicopter conducting wildfire response operations in proximity to an area in which simulated small UAS, supported by UTM services, were conducting prescribed burn operations.
An advanced preprototype Thermoelectric Integrated Membrane Evaporation Subsystem (TIMES) has been developed to provide high quality water recovery from various types of wastewater on extended duration space flights. The subsystem has undergone extensive wastewater processing testing, in order to evaluate its potential as an essential part of the Space Station Water Reclamation System. A discussion of the operating performance of the TIMES is presented in this paper, with special attention given to the water quality attained for a number of simulated Space Station wastewater feedstocks.
Integrated System Health Management (ISHM) is a capability that focuses on determining the condition (health) of every element in a complex System (detect anomalies, diagnose causes, prognosis of future anomalies), and provide data, information, and knowledge (DIaK)-not just data-to control systems for safe and effective operation. This capability is currently done by large teams of people, primarily from ground, but needs to be embedded on-board systems to a higher degree to enable NASA's new Exploration Mission (long term travel and stay in space), while increasing safety and decreasing life cycle costs of spacecraft (vehicles; platforms; bases or outposts; and ground test, launch, and processing operations). The topics related to this capability include: 1) ISHM Related News Articles; 2) ISHM Vision For Exploration; 3) Layers Representing How ISHM is Currently Performed; 4) ISHM Testbeds & Prototypes at NASA SSC; 5) ISHM Functional Capability Level (FCL); 6) ISHM Functional Capability Level (FCL) and Technology Readiness Level (TRL); 7) Core Elements: Capabilities Needed; 8) Core Elements; 9) Open Systems Architecture for Condition-Based Maintenance (OSA-CBM); 10) Core Elements: Architecture, taxonomy, and ontology (ATO) for DIaK management; 11) Core Elements: ATO for DIaK Management; 12) ISHM Architecture Physical Implementation; 13) Core Elements: Standards; 14) Systematic Implementation; 15) Sketch of Work Phasing; 16) Interrelationship Between Traditional Avionics Systems, Time Critical ISHM and Advanced ISHM; 17) Testbeds and On-Board ISHM; 18) Testbed Requirements: RETS AND ISS; 19) Sustainable Development and Validation Process; 20) Development of on-board ISHM; 21) Taxonomy/Ontology of Object Oriented Implementation; 22) ISHM Capability on the E1 Test Stand Hydraulic System; 23) Define Relationships to Embed Intelligence; 24) Intelligent Elements Physical and Virtual; 25) ISHM Testbeds and Prototypes at SSC Current Implementations; 26) Trailer-Mounted RETS; 27) Modeling and Simulation; 28) Summary ISHM Testbed Environments; 29) Data Mining - ARC; 30) Transitioning ISHM to Support NASA Missions; 31) Feature Detection Routines; 32) Sample Features Detected in SSC Test Stand Data; and 33) Health Assessment Database (DIaK Repository).
The Integration of Automated Systems (IAS) Project is conducting a series of 2023 flight tests supporting NASA's Advanced Air Mobility (AAM) and National Campaign efforts. These flights include crewed, test (i.e., ownship) and traffic (i.e., intruder) aircraft that will fly with unique technologies onboard. The presentation will include overviews of the Hazard Perception and Avoidance (HPA) and Flight Path Management (FPM) technical areas but will focus primarily on HPA. HPA will test the FAA's Airborne Collision Avoidance System X (ACAS X), a next-generation collision avoidance tool developed to support different aircraft types and operations. The rotorcraft variant, ACAS Xr, is designed to accommodate existing helicopter platforms and in-development, vertical takeoff and landing (VTOL) concepts, which are critical to the emerging AAM concept of operations. Two configurations of ACAS Xr will be examined: Collision Avoidance System (CAS, similar to the Traffic Collision Avoidance System [TCAS] II) and Detect and Avoid (DAA, previously developed to provide added situational awareness for uncrewed aircraft). Additionally, this system will be explored during cruise and low-speed flight as well as flights within en-route, structured (i.e., dense/urban), and terminal airspaces. Scripted flight conflicts will be conducted, and these conflicts will be mitigated through maneuvers that are manual (i.e., performed by the pilots) or automated (i.e., achieved by the cooperation of the program middleware and onboard ownship systems). Objective data will be collected involving system and pilot performance as well as pilot decisions; subjective data will include pilot opinions of ACAS Xr's alerting and guidance as well as the automated maneuvers.
This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.
With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire -bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500°C are reviewed.
With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3 ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3 ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire - bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500oC are reviewed.
Integrated Reaction Control Systems (IRCS) are considered an enabling technology for future human exploration of the solar system. An IRCS uses the same fuel and oxidizer as the main propulsion system, allowing for increased performance and simplified cryogenic fluid management operations. The IRCS team at Marshall Spaceflight Center is currently evaluating an IRCS system that uses a combination of electric pumps and pressure-regulation devices to provide a constant flow of conditioned propellant to a thruster bank during operation. In contrast to accumulator and gasifier designs, the recirculation loop design is less massive and can provide large, sustained flowrates to the thruster inlet. In the summer 2021 test series presented herein, the feasibility of this concept was evaluated using liquid nitrogen as a simulant for liquid oxygen. The goals of this test series were to demonstrate the ability of the pump and pressure regulator to maintain adequate thruster inlet conditions during transient operation, and to demonstrate the ability for the system to operate in an “idle mode” that maintains system chill between activations. During test operations, the back-pressure regulator responded more slowly than the opening/closing of valves in the thruster simulant, but it was still able to attenuate the pressure fluctuation at the pump discharge and ensure a stable flowrate through the pump. Similarly, the pump was able to be run far below its nominal operating point and successfully flow sufficient fluid to maintain chill conditions.