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At least 775 records · Page 43

Accelerating DCA++ (Dynamical Cluster Approximation) Scientific Application on the Summit supercomputer

Optimizing scientific applications on today’s accelerator-based high performance computing systems can be challenging, especially when multiple GPUs and CPUs with heterogeneous memories and persistent non-volatile memories are present. An example is Summit, an accelerator-based system at the Oak Ridge Leadership Computing Facility (OLCF) that is rated as the world’s fastest supercomputer to-date. New strategies are thus needed to expose the parallelism in legacy applications, while being amenable to efficient mapping to the underlying architecture.In this paper we discuss our experiences and strategies to port a scientific application, DCA++, to Summit. DCA++ is a highperformance research application that solves quantum manybody problems with a cutting edge quantum cluster algorithm, the dynamical cluster approximation.Our strategies aim to synergize the strengths of the different programming models in the code. These include: (a) streamlining the interactions between the CPU threads and the GPUs, (b) implementing computing kernels on the GPUs and decreasing CPU-GPU memory transfers, (c) allowing asynchronous GPU communications, and (d) increasing compute intensity by combining linear algebraic operations.Full-scale production runs using all 4600 Summit nodes attained a peak performance of 73.5 PFLOPS with a mixed precision implementation.We observed a perfect strong and weak scaling for the quantum Monte Carlo solver in DCA++, while encountering about 2× input/output (I/O) and MPI communication overhead on the time-to-solution for the full machine run. Our hardware agnostic optimizations are designed to alleviate the communication and I/O challenges observed, while improving the compute intensity and obtaining optimal performance on a complex, hybrid architecture like Summit.

Balduzzi, Giovanni↗

Status and Challenges of the Interaction Region Magnets for HL-LHC

About one hundred magnets of six different types shall be installed in the High Luminosity LHC (HL-LHC) in the years 2026-2028 at CERN. The magnets design, construction and test are based on CERN collaborations with institutes and industrial partners in USA, Spain, Italy, Japan and China. Three types of correctors are based on Nb-Ti technology and feature conductor peak fields in the 2 to 4 T range: for all of them the prototype phase has been successfully completed. The production is well advanced for the superferric correctors, and is starting for the canted cosine theta correctors and for the nested correctors. The separation and recombination Nb-Ti dipoles D1 and D2, with a 4.5-6 T bore field range, are both in the prototype phase after the completion of the short model program. The most challenging magnet, the Nb 3 Sn quadrupole with conductor peak field above 11 T, is in the prototype phase at CERN and halfway through the production phase in the USA. In this paper we will give, for each type of magnet, an overview of the main achievements obtained so far and we will outline the technical points still needing validation from the prototype program.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

The Quench Protection of Direct Wind Magnets

The direct wind magnets have several unique features. The conductor layout is characterized by thin single conductors wound over long lengths and separated from the other turns with thick layer of insulation. Moreover, there are several layers of winding. The strong non-uniformity in the magnetic field distribution results in different current and thermal margins for quenching in different regions. The quench protection modeling involves multi-physics coupling between electrical, thermal and magnetic transient. The material properties vary over time and location. This coupled with the complexity in the geometry adds to long computation times. The objective of this study is to understand the quench propagation in an EIC high inductance direct wind magnet which enables one to design appropriate quench protection strategies to protect the magnet. An advanced modeling program has been developed to simulate direct wind magnet quench. In conclusion, we validate theoretical simulations with experimental data.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Logically Parallel Communication for Fast MPI+Threads Applications

Supercomputing applications are increasingly adopting the MPI+threads programming model over the traditional "MPI everywhere" approach to better handle the disproportionate increase in the number of cores compared with other on-node resources. In practice, however, most applications observe a slower performance with MPI+threads primarily because of poor communication performance. Recent research efforts on MPI libraries address this bottleneck by mapping logically parallel communication, that is, operations that are not subject to MPI's ordering constraints to the underlying network parallelism. Domain scientists, however, typically do not expose such communication independence information because the existing MPI-3.1 standard's semantics can be limiting. Researchers had initially proposed user-visible endpoints to combat this issue, but such a solution requires intrusive changes to the standard (new APIs). The upcoming MPI-4.0 standard, on the other hand, allows applications to relax unneeded semantics and provides them with many opportunities to express logical communication parallelism. Here in this article, we show how MPI+threads applications can achieve high performance with logically parallel communication. Through application case studies, we compare the capabilities of the new MPI-4.0 standard with those of the existing one and user-visible endpoints (upper bound). Logical communication parallelism can boost the overall performance of an application by over 2x.

97 MATHEMATICS AND COMPUTING↗

ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing

The next generation HPC and data centers are likely to be reconfigurable and data-centric due to the trend of hardware specialization and the emergence of data-driven applications. In this work, we propose ARENA – an asynchronous reconfigurable accelerator ring architecture as a potential scenario on how the future HPC and data centers will be like. Despite using the coarse-grained reconfigurable arrays (CGRAs) as the substrate platform, our key contribution is not only the CGRA-cluster design itself, but also the ensemble of a new architecture and programming model that enables asynchronous tasking across a cluster of reconfigurable nodes, so as to bring specialized computation to the data rather than the reverse. We presume distributed data storage without asserting any prior knowledge on the data distribution. Hardware specialization occurs at runtime when a task finds the majority of data it requires are available at the present node. In other words, we dynamically generate specialized CGRA accelerators where the data reside. The asynchronous tasking for bringing computation to data is achieved by circulating the task token, which describes the dataflow graphs to be executed for a task, among the CGRA cluster connected by a fast ring network. Evaluations on a set of HPC and data-driven applications across different domains show that ARENA can provide better parallel scalability with reduced data movement (53.9 percent). Compared with contemporary compute-centric parallel models, ARENA can bring on average 4.37× speedup. The synthesized CGRAs and their task-dispatchers only occupy 2.93mm 2 chip area under 45nm process technology and can run at 800MHz with on average 759.8mW power consumption. ARENA also supports the concurrent execution of multi-applications, offering ideal architectural support for future high-performance parallel computing and data analytics systems.

97 MATHEMATICS AND COMPUTING↗

A Data-Driven Methodology for Contextual Unit Commitment Using Regression Residuals

Day after day, system operators are faced with the challenge of taking unit commitment (UC) decisions under uncertain net load conditions. The standard operating procedure for taking UC decisions begins by leveraging auxiliary data on covariates (such as the day of the week or latest weather information) to generate a point prediction for net load, which is used in solving a deterministic UC problem. Such an approach, however, is known to deliver a notoriously poor out-of-sample (OOS) performance, as it completely disregards the stochastic nature of net load. While stochastic programming models explicitly represent uncertainty, they mostly do so using a generic set of scenarios that neglect covariate observations, squandering useful auxiliary data that could be harnessed to glean insights into uncertainty. In this article, we discuss a contextual stochastic optimization approach to UC, which effectively exploits covariate observations while explicitly assessing uncertainty so as to boost the OOS performance of UC decisions. The key thrust of our approach is to leverage regression models, along with their empirical residuals, to set up and solve sample average approximation problems. Not only do we prove that our approach satisfies the requisite conditions for asymptotic optimality and consistency laid out in (Kannan et al., 2022), but we also assess its performance on several case studies conducted using real-world data collected in California ISO and New York ISO grids. In conclusion, results show that the proposed approach can significantly improve OOS performance compared to alternative methods proposed in the literature under varying dataset sizes.

Yurdakul, Ogun↗

Self-Healing Attack-Resilient PMU Network for Power System Operation

In this paper, we propose a self-healing phasor measurement unit (PMU) network that exploits the features of dynamic and programmable configuration in a software-defined networking infrastructure to achieve resiliency against cyber-attacks. After a cyber-attack, the configuration of network switches is changed to isolate the compromised PMUs/phasor data concentrators to prevent further propagation of the attack; meanwhile, the disconnected yet uncompromised PMUs will be reconnected to the network to "self-heal" and thus restore the observability of the power system. Specifically, we formulate an integer linear programming model to minimize the overhead of the self-healing process (e.g., the recovery latency), while considering the constraints of power system observability, hardware resources, and network topology. We also propose a heuristic algorithm to decrease the computational complexity. Case studies of a PMU network based on the IEEE 30-bus and 118-bus systems are used to validate the effectiveness of the self-healing mechanism.

Cybersecurity↗

Impacts of Integrating Topology Reconfiguration and Vehicle-to-Grid Technologies on Distribution System Operation

Autonomous electric vehicles (AEVs) provide unique opportunities to cope with the uncertainties of distributed energy generation in distribution networks. But the effects are limited by both inherent radial topology and the behaviors of decentralized AEVs. As such, we investigate the potential benefits of dynamic distribution network reconfiguration (DDNR), taking into account AEVs' spatial-temporal availability and their charging demand. We propose a mixed integer programming model to optimally coordinate the charging/discharging of AEVs with DDNR, while satisfying AEVs' original travel plan. Numerical studies based on a test system overlaying the IEEE 33-node test feeder and Sioux Falls transportation network show that DDNR and AEV complement each other, which improves the operation of the distribution system. We also conduct sensitivity analyses on inputs including renewable fluctuation and AEVs penetration level.

33 ADVANCED PROPULSION SYSTEMS↗

Analysis of Validating and Verifying OpenACC Compilers 3.0 and Above

OpenACC is a high-level directive-based parallel programming model that can manage the sophistication of heterogeneity in architectures and abstract it from the users. The portability of the model across CPUs and accelerators has gained the model a wide variety of users. This means it is also crucial to analyze the reliability of the compilers’ implementations. To address this challenge, the OpenACC Validation and Verification team has proposed a validation testsuite to verify the OpenACC implementations across various compilers with an infrastructure for a more streamlined execution. This paper will cover the following aspects: (a) the new developments since the last publication on the testsuite, (b) outline the use of the infrastructure, (c) discuss tests that highlight our workflow process, (d) analyze the results from executing the testsuite on various systems, and (e) outline future developments.

Jarmusch, Aaron↗

On-Sun Testing of a High-Temperature Solar Receiver's Flux Distribution

Concentrated solar power (CSP) is a promising technology in transitioning to renewable energy because of its abundance in nature and thermal energy storage (TES) capability. Among the four types of available CSP technology, including parabolic trough, linear Fresnel, power tower, and parabolic dishes, a power tower using a central receiver has more potential to generate high-temperature heat in a scale supporting power cycles efficiency and achieve low levelized cost of energy (LCOE). Other than the conventional type of receiver design, the high-absorptive receiver concept developed and presented in this paper is novel in its design approach. The novel receiver design originated from National Renewable Energy Laboratory (NREL) consists of an array of solar flux absorb tubes. The solar absorb tubes require uniform flux distribution and in-depth flux penetration through the three different reflective sections of tubes in a hexagonal shape. To evaluate this unique receiver design and thermal performance, the flux distribution, flux uniformity, and intensity were numerically simulated using ansys fluent and SolTrace modeling program. On-sun testing has been done at NREL high flux solar testing facility, based on the computational analysis.

clean energy↗

SU-F-E-13: Design and Fabrication of Gynacological Brachytherapy Shielding & Non Shielding Applicators Using Indigenously Developed 3D Printing Machine

Purpose: In this innovative work we have developed Gynecological Brachytherapy shielding & Non Shielding Applicators and compared with the commercially available applicators by using the indigenously developed 3D Printing machine. Methods: We have successfully indigenously developed the 3D printing machine. Which contain the 3 dimensional motion platform, Heater unit, base plate, ect… To fabricate the Gynecological Brachytherapy shielding & non shielding applicators the 3D design were developed in the computer as virtual design. This virtual design is made in a CAD computer file using a 3D modeling program. Separate programme for the shielding & non shielding applicators. We have also provided the extra catheter insert provision in the applicator for the multiple catheter. The DICOM file of the applicator were then converted to stereo Lithography file for the 3D printer. The shielding & Non Shielding Applicators were printed on a indigenously developed 3D printer material. The same dimensions were used to develop the applicators in the acrylic material also for the comparative study. A CT scan was performed to establish an infill-density calibration curve as well as characterize the quality of the print such as uniformity and the infill pattern. To commission the process, basic CT and dose properties of the printing materials were measured in photon beams and compared against water and soft tissue. Applicator were then scanned to confirm the placement of multiple catheter position. Finally dose distributions with rescanned CTs were compared with those computer-generated applicators. Results: The doses measured from the ion Chamber and X-Omat film test were within 2%. The shielded applicator reduce the rectal dose comparatively with the non shielded applicator. Conclusion: As of submission 3 unique cylinders have been designed, printed, and tested dosimetrically. A standardizable workflow for commissioning custom 3D printed applicators was codified and will be reported.

60 APPLIED LIFE SCIENCES↗

A Performance Portable, Fully Implicit Landau Collision Operator with Batched Linear Solvers

Modern accelerators use hierarchical parallel programming models that enable massive multithreading within a processing element (PE), with multiple PEs per device driven by traditional processes. Batching is a technique for exposing PE-level parallelism in algorithms that have traditionally run on MPI processes or multiple threads within a single process. Opportunities for batching arise in, for example, kinetic discretizations of magnetized plasmas where collisions are advanced in velocity space at each spatial point independently. This paper builds on previous work on a high-performance, fully nonlinear, Landau collision operator by batching the linear solver, as well as batching the spatial point problems and adding new support for multiple grids for multiscale, multispecies problems. An anisotropic relaxation verification test that agrees well with previously published results and analytical models is presented. The performance results from NVIDIA A100 and AMD MI250X nodes are presented with hardware utilization analysis for each architecture. Finally, the entire implicit Landau operator time advance is implemented in Kokkos for performance portability, running entirely on the device and is available in the PETSc numerical library.

97 MATHEMATICS AND COMPUTING↗

Makalu: fast recoverable allocation of non-volatile memory

Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive and a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.

97 MATHEMATICS AND COMPUTING↗

User-Assisted Store Recycling for Dynamic Task Graph Schedulers

The emergence of the multi-core era has led to increased interest in designing effective yet practical parallel programming models. Models based on task graphs that operate on single-assignment data are attractive in several ways: they can support dynamic applications and precisely represent the available concurrency. However, they also require nuanced algorithms for scheduling and memory management for efficient execution. In this paper, we consider memory-efficient dynamic scheduling of task graphs. Specifically, we present a novel approach for dynamically recycling the memory locations assigned to data items as they are produced by tasks. We develop algorithms to identify memory-efficient store recycling functions by systematically evaluating the validity of a set of (user-provided or automatically generated) alternatives. Because recycling function can be input data-dependent, we have also developed support for continued correct execution of a task graph in the presence of a potentially incorrect store recycling function. Experimental evaluation demonstrates that our approach to automatic store recycling incurs little to no overheads, achieves memory usage comparable to the best manually derived solutions, often produces recycling functions valid across problem sizes and input parameters, and efficiently recovers from an incorrect choice of store recycling functions.

97 MATHEMATICS AND COMPUTING↗

Evaluating the Performance of Integer Sum Reduction in SYCL on GPUs

SYCL is a promising programming model for heterogeneous computing—allowing a single-source code to target devices from multiple vendors. One significant task performed on these accelerators is a primitive operation for integer sum reduction. This paper presents several SYCL implementations of integer sum reduction—using atomic functions, shared local memory, vectorized memory accesses and parameterized workload sizes—to compare the performance and maturity of SYCL against open-source vendor-specific implementations of the same reduction. For a sufficiently large number of integers, tuning the parameters of our SYCL implementations achieves 1.4X speedup over the open-source implementations on an Intel UHD630 integrated GPU. The SYCL reduction is 3% faster than the templated reduction in Thrust, and 0.3% faster than the device reduction in CUB on an Nvidia P100 GPU. The SYCL reduction is 1.9% faster than the templated reduction in Thrust, and 0.4% faster than the device reduction in CUB on an Nvidia V100 GPU.

Jin, Zheming↗

Fast and Scalable Sparse Triangular Solver for Multi-GPU Based HPC Architectures

Designing efficient and scalable sparse linear algebra kernels on modern multi-GPU based HPC systems is a daunting task due to significant irregular memory references and workload imbalance across the GPUs. This is particularly the case for \textit{Sparse Triangular Solver (SpTRSV)} which introduces additional two-dimensional computation dependencies among subsequent computation steps. Dependency information is exchanged and shared among GPUs, thus warrant for efficient memory allocation, data partitioning, and workload distribution as well as fine-grained communication and synchronization support. In this work, we demonstrate that directly adopting unified memory can adversely affect the performance of SpTRSV on multi-GPU architectures, despite linking via fast interconnect like NVLinks and NVSwitches. Alternatively, we employ the latest NVSHMEM technology based on Partitioned Global Address Space programming model to enable efficient fine-grained communication and drastic synchronization overhead reduction. Furthermore, to handle workload imbalance, we propose a malleable task-pool execution model which can further enhance the utilization of GPUs. By applying these techniques, our experiments on the NVIDIA multi-GPU supernode V100-DGX-1 and DGX-2 systems demonstrate that our design can achieve on average 3.53x (up to 9.86x) speedup on a DGX-1 system and 3.66x (up to 9.64x) speedup on a DGX-2 system with 4-GPUs over the Unified-Memory design. The comprehensive sensitivity and scalability studies also show that the proposed zero-copy SpTRSV is able to fully utilize the computing and communication resources of the multi-GPU system.

Xie, Chenhao↗