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At least 865 records · Page 48

Highly scalable distributed-memory sparse triangular solution algorithms.

This paper presents a highly efficient distributed-memory parallel sparse triangular solver. The triangular solution phase is often performed following factorization phase in the sparse linear solvers and has become increasingly computa­tionally expensive for direct solvers with many right hand sides (RHSs) or preconditioned iterative solvers. However, the low arithmetic intensity and sequential nature of the triangular solve algorithm pose performance challenges for its large-scale distributed-memory parallelization. In this work, we propose several strategies to enhance scalability of an algorithm with 2D block cyclic process layout. First, an asynchronous binary-tree-based communication scheme implemented via non-blocking MPI functions is leveraged to broadcast partial solutions and reduce partial updates among a subset of processes for each block column and row of the triangular matrix, respectively. This scheme reduces message latency, improves communication load balance and significantly accelerates asynchronous execution of the triangular solve. In addition, efficient BLAS operations and threading implementations are exploited to accelerate local computations and further reduce process idle time. The proposed strategies are implemented in SuperLU_DIST and numerical experiments show up to 4.4x improvement with one right-hand side and up to 6.1x improvement with 50 right- hand sides on 4096 processes, compared to the current release. This is the first time that sparse triangular solution is demonstrated strong scaling on more than 4000 cores.

Liu, Yang↗

Randomized Sketching Algorithms for Low-Memory Dynamic Optimization

This paper develops a novel limited-memory method to solve dynamic optimization problems. The memory requirements for such problems often present a major obstacle, particularly for problems with PDE constraints such as optimal flow control, full waveform inversion, and optical tomography. In these problems, PDE constraints uniquely determine the state of a physical system for a given control; the goal is to find the value of the control that minimizes an objective. While the control is often low dimensional, the state is typically more expensive to store. This paper suggests using randomized matrix approximation to compress the state as it is generated and shows how to use the compressed state to reliably solve the original dynamic optimization problem. Concretely, the compressed state is used to compute approximate gradients and to apply the Hessian to vectors. The approximation error in these quantities is controlled by the target rank of the sketch. This approximate first- and second-order information can readily be used in any optimization algorithm. As an example, we develop a sketched trust-region method that adaptively chooses the target rank using a posteriori error information and provably converges to a stationary point of the original problem. Numerical experiments with the sketched trust-region method show promising performance on challenging problems such as the optimal control of an advection-reaction-diffusion equation and the optimal control of fluid flow past a cylinder.

97 MATHEMATICS AND COMPUTING↗

BonVoision: Leveraging Spatial Data Smoothness For Recovery From Memory Soft Errors

The increasing soft error rates in memory systems raise an emerging concern for modern computing systems. As a result, detectable but uncorrectable errors (DUEs) become potentially more frequent and affect HPC applications. Today, upon encountering a DUE, HPC applications crash, incurring significant performance, storage, and energy overheads. In this paper, we propose a technique to continue application execution past a DUE through the repair of the corrupted memory data by leveraging spatial data smoothness. We present BonVoision, a run-time system that intercepts DUE events, analyzes the binary to identify data elements in the structural neighborhood of the event, and fixes the corrupted data elements by interpolating from the values in their neighborhood. Our evaluation demonstrates that BonVoision incurs negligible overhead and outperforms other recovery strategies by a factor of 2×, on average. We demonstrate that BonVoision also improves the efficiency of existing checkpointing/restart schemes by approximately increasing the optimal checkpoint interval by 23%.

Fang, Bo↗

CoREC: Scalable and Resilient In-memory Data Staging for In-situ Workflows

The dramatic increase in the scale of current and planned high-end HPC systems is leading new challenges, such as the growing costs of data movement and IO, and the reduced mean time between failures (MTBF) of system components. In-situ workflows, i.e., executing the entire application workflows on the HPC system, have emerged as an attractive approach to address data-related challenges by moving computations closer to the data, and staging-based frameworks have been effectively used to support in-situ workflows at scale. However, the resilience of these staging-based solutions has not been addressed, and they remain susceptible to expensive data failures. Furthermore, naive use of data resilience techniques such as n-way replication and erasure codes can impact latency and/or result in significant storage overheads. In this article, we present CoREC, a scalable and resilient in-memory data staging runtime for large-scale in-situ workflows. CoREC uses a novel hybrid approach that combines dynamic replication with erasure coding based on data access patterns. It also leverages multiple levels of replications and erasure coding to support diverse data resiliency requirements. Furthermore, the article presents optimizations for load balancing and conflict-avoiding encoding, and a low overhead, lazy data recovery scheme. We have implemented the CoREC runtime and have deployed with the DataSpaces staging service on leadership class computing machines and present an experimental evaluation in the article. Here, the experiments demonstrate that CoREC can tolerate in-memory data failures while maintaining low latency and sustaining high overall storage efficiency at large scales.

97 MATHEMATICS AND COMPUTING↗

Timely Reporting of Heavy Hitters Using External Memory

Given an input stream S of size N, a Φ-heavy hitter is an item that occurs at least ΦN times in S. The problem of finding heavy-hitters is extensively studied in the database literature. In this work, we study a real-time heavy-hitters variant in which an element must be reported shortly after we see its T = Φ N-th occurrence (and hence it becomes a heavy hitter). We call this the Timely Event Detection (TED) Problem. The TED problem models the needs of many real-world monitoring systems, which demand accurate (i.e., no false negatives) and timely reporting of all events from large, high-speed streams with a low reporting threshold (high sensitivity). Like the classic heavy-hitters problem, solving the TED problem without false-positives requires large space (Ω (N) words). Thus in-RAM heavy-hitters algorithms typically sacrifice accuracy (i.e., allow false positives), sensitivity, or timeliness (i.e., use multiple passes). We show how to adapt heavy-hitters algorithms to external memory to solve the TED problem on large high-speed streams while guaranteeing accuracy, sensitivity, and timeliness. Our data structures are limited only by I/O-bandwidth (not latency) and support a tunable tradeoff between reporting delay and I/O overhead. With a small bounded reporting delay, our algorithms incur only a logarithmic I/O overhead. We implement and validate our data structures empirically using the Firehose streaming benchmark. Multi-threaded versions of our structures can scale to process 11M observations per second before becoming CPU bound. In comparison, a naive adaptation of the standard heavy-hitters algorithm to external memory would be limited by the storage device’s random I/O throughput, i.e., ≈100K observations per second.

97 MATHEMATICS AND COMPUTING↗

Synchronization for CXL Based Memory

Compute Express Link (CXL) is an important emerging standard for disaggregated memory. While this standard provisions coherency across numerous hosts and devices, implementing hardware support for type three devices is challenging. In this work, we look at the overhead of software synchronization and using software-based coherency. Moreover, we discuss the limits of software-based coherency in fully expressing modern synchronization techniques for a CXL-based disaggregate memory system. We demonstrate our approach using a CXL hardware prototype and running a version of the famous Peterson Lock (enhanced to run with more than two threads). We analyze its performance and share how more advanced synchronization techniques might interact with software-based coherence CXL hardware and program execution models.

High Performance Computing (HPC)↗

Studying CPU and memory utilization of applications on Fujitsu A64FX and Nvidia Grace Superchip

ARM-based manycore CPU architectures are well-positioned to provide the rising memory throughput requirements of modern data intensive scientific applications in High Performance Computing (HPC). The Fujitsu A64FX CPU platform is based on the ARM v8.2A architecture, and is the processor of the flagship Japanese supercomputer - "Fugaku", which was previously ranked as the #1 supercomputer in the world according to the Top500 list. The Nvidia Grace superchip features 144 Neoverse V2 cores based on the ARMv9 architecture with 4x128b SVE2, providing exceptional computational power. The chip supports up to 480GB of memory, making it ideal for AI, machine learning, and scientific computing workloads. In this paper, we conduct a thorough performance exploration of a variety of parallel bandwidth-sensitive benchmarks and applications compiled with the native Fujitsu compiler on a Fugaku A64FX compute node and ARM (LLVM) Compiler on an NVIDIA Grace superchip compute node, engaging all the computational cores per cluster using OpenMP multithreading (assuming the cores can drive the available bandwidth). Our ultimate goals are to study the resource utilization of scientific applications and benchmarks on A64FX and Grace superchip, considering graph application scenarios ( GAP Benchmark suite) and eleven appli- cation proxies from the Rodinia heterogeneous benchmark suite (considering domains such as Data Mining, Bioinformatics, Fluid Dynamics, Pattern Recognition, etc.). Through exhaustive performance monitoring, we quantify the resource utilization of diverse OpenMP-based HPC applications on both the Fujitsu A64FX and the Nvidia Grace Superchip platforms.

benchmarking, Performance Analysis, High performan↗

Memory Analysis Tool

This tool traces all memory accesses to stack (static allocation) and heap (dynamic allocation) on a trace run in a particular hardware and then estimates execution time on given arbitrary hardware configurations for hardware design space exploration. It can also compute memory access statistics, such as reuse distance.

Sato, Kento↗

High-temperature superelasticity in NiTiPt and NiTiPd shape memory alloys

Alloying NiTi shape memory alloys with sufficient Pt and Pd at the expense of Ni has been shown to increase transformation temperatures well above those possible with the binary composition, enabling consideration of a new class of high-temperature mechanical sensors and actuators. To achieve shape memory behavior at temperatures greater than 200 °C, previous studies of NiTiPt and NiTiPd compositions have focused primarily on alloys with greater than 16 at.% Pt and 25 at.% Pd. While generally not the focus, none of these previous studies demonstrated superelastic behavior at high temperatures. In an effort to identify alloys that transform to austenite at approximately 200 °C and exhibit superelastic behavior with recoverable strains greater than 2%, a series of Ti-rich NiTiPt ternary alloys with 15.5–16.5 at.% Pt, and Ti-rich NiTiPd ternary alloys with 25–26 at.% Pd have been targeted. The polycrystalline alloys were processed via arc melting followed by homogenization heat treatment. Thermomechanical properties were measured using electro-discharge machined tension test coupons and a miniature load frame equipped with a clamshell furnace. Ultimately, superelasticity in uniaxial tension with clear plateau regions was demonstrated and characterized in these alloys at temperatures between 219 °C and 270 °C.

Massad, Jordan E.↗

Memory and CPU efficient coherent mode decomposition of partially coherent synchrotron radiation with subtraction of common quadratic phase terms

Application examples of a memory and CPU efficient coherent mode decomposition (CMD) method for wave-optics based simulation of the partially coherent undulator radiation propagation through a hard X-ray beamline in a 3rd generation synchrotron radiation source are presented. The high efficiency of the method is achieved thanks to the analytical treatment of the common quadratic phase terms that are developed in the phase of cross-spectral density (CSD) of partially coherent radiation at a distance from source. This treatment allows for a considerable, several orders of magnitude, reduction of the 4D CSD mesh density (and the memory occupied by the CSD) required for ensuring sufficient accuracies of wavefront propagation simulations with the modes produced by the CMD at a beamline entrance. This method, implemented in the “Synchrotron Radiation Workshop” open-source software, dramatically increases the feasibility of the CMD of 4D CSD for producing 2D coherent modes for a large variety of applications at storage rings and other types of radiation sources.

36 MATERIALS SCIENCE↗

Improving Physics Based Electron Neutrino Appearance Identication with a Long Short-Term Memory Network

The NOvA experiment is a long baseline neutrino oscillation experiment with the objective to measure the oscillation probability of muon type neutrinos ($\nu_{\mu}$) into electron type neutrinos ($\nu_e$). NOvA measures the interactions of neutrinos from the NuMI beam in two functionally identical liquid scintillator detectors. The far detector detects the appearance of electron neutrinos, leading to measurement of the oscillation parameters under study. Using an off -axis beam with an 810 km baseline length, NOvA is sensitive to measuring the neutrino mass hierarchy, the CP violating parameter, and the octant of the mixing angle, $\theta_{23}$. The data presented in this thesis has been collected from October 2013 until May 2018. The first NOvA $\nu_e$ charged current identifier utilized an artificial neural network with the physical features of the highest energy reconstructed shower as inputs. The $\nu_ e$ charged current identifier in this thesis utilizes a Long Short-Term Memory network with the physical features of every reconstructed shower in a particular interaction. In addition to the Long Short-Term Memory network, there are two Boosted Decision Trees to assist in event level selection. In the analysis of the data, 54 $\nu_e$ candidate events were detected with an expected background of 15 events. The results of this analysis prefer the normal mass hierarchy with maximal mixing and $\frac{\delta_{CP}}{\pi}=1.92_{-1.19}^{0.08}$. Results from this analysis differ from the published NOvA analysis, due to the differences of electron identification techniques.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

Sparse Data Acquisition on Emerging Memory Architectures

Emerging memory devices, such as resistive crossbars, have the capacity to store large amounts of data in a single array. Acquiring the data stored in large-capacity crossbars in a sequential fashion can become a bottleneck. We present practical methods, based on sparse sampling, to quickly acquire sparse data stored on emerging memory devices that support the basic summation kernel, reducing the acquisition time from linear to sub-linear. Experimental results show that at least an order of magnitude improvement in acquisition time can be achieved when the data is sparse.

97 MATHEMATICS AND COMPUTING↗

Multi-Level Memory Algorithmics for Large, Sparse Problems

In this report, we abstract eleven papers published during the project and describe preliminary unpublished results that warrant follow-up work. The topic is multi-level memory algorithmics, or how to effectively use multiple layers of main memory. Modern compute nodes all have this feature in some form.

97 MATHEMATICS AND COMPUTING↗

Understanding Data Structures by Extracting Memory Access Graphs

Understanding the data structures employed by a program is important for reverse engineering activities and can improve the results of automated software analysis techniques. In a compiled binary, access to data structure fields and array indices defined in the source program are replaced by raw pointer arithmetic. We present a representation for capturing the essential details of how a program accesses memory regions, which we call a Memory Access Graph (MAG), and a static analysis for automatically extracting this information from a program binary. The static analysis to extract the MAGs from the program is straightforward and does not require sophisticated integer or pointer analysis. The MAGs are readily understood by reverse engineers; they are generally able to perceive the data structure definition corresponding to a MAG. We briefly discuss automatic extraction of structure definitions outlining some of the difficulties in doing so.

97 MATHEMATICS AND COMPUTING↗

Unified Memory: GPGPU-Sim/UVM Smart Integration

CPU/GPU heterogeneous compute platforms are an ubiquitous element in computing and a programming model specified for this heterogeneous computing model is important for both performance and programmability. A programming model that exposes the shared, unified, address space between the heterogeneous units is a necessary step in this direction as it removes the burden of explicit data movement from the programmer while maintaining performance. GPU vendors, such as AMD and NVIDIA, have released software-managed runtimes that can provide programmers the illusion of unified CPU and GPU memory by automatically migrating data in and out of the GPU memory. However, this runtime support is not included in GPGPU-Sim, a commonly used framework that models the features of a modern graphics processor that are relevant to non-graphics applications. UVM Smart was developed, which extended GPGPU-Sim 3.x to in- corporate the modeling of on-demand pageing and data migration through the runtime. This report discusses the integration of UVM Smart and GPGPU-Sim 4.0 and the modifications to improve simulation performance and accuracy.

97 MATHEMATICS AND COMPUTING↗

Controlling reversible phase transitions in rare-earth nickelates for novel memory devices

Resistive switching in correlated complex oxides is lucrative for emerging applications in neuromorphic computing, and densely scaled non-volatile memory. Electrical conductance of such complex oxides can be controllable switched across multiple orders of magnitude by either (a) electroforming a conduction channel (e.g., in tungsten oxide), or (b) inducing Mott-Hubbard transition (e.g., in rare-earth nickelates)– both via controlled migration of defects (such as oxygen vacancies) under applied bias. Nevertheless, the promise of such defect-driven electronic transitions are far from realized due to a lack of fundamental understanding of the atomic-scale processes that underlie migration and spatiotemporal evolution of oxygen vacancies over nano-to-mesoscopic length/timescales under applied electric field. In this project, we employ a synergistic integration of density functional theory (DFT) calculations, ab initio/classical molecular dynamics (AIMD/CMD) simulations, machine learning (ML), precision synthesis, and multi-modal X-ray imaging experiments to address this knowledge gap. Such an integrated approach offers to elucidate the correlations between subtle structural distortion and oxidation states; treat localized charge carriers; describe defect/ion transport in the presence of electric field; and, in turn, greatly advance the current understanding of microstructural evolution in complex oxides under applied bias. The fundamental knowledge gained from this work will enable precise control over hierarchical defect structures and unravel new routes to manipulate resistance states in complex oxides. This, in turn, will accelerate design of novel devices with desired set of neural functionalities, and high-speed densely-scaled resistive random access memory technologies.

36 MATERIALS SCIENCE↗

Multifunctional Fiber-Reinforced Polymer Composites for Damage Detection and Memory

Self-structural health monitoring (SHM) functionalities for fiber-reinforced polymer composites have become highly sought after to ensure the structural safety of newly advancing components in the automotive, civil, mechanical, and aerospace industries. This paper introduces a self-damage detection and memory (SDDM) hybrid composite material, where the structural carbon fiber tow is transformed into a piezoresistive sensor network, and the structural glass fiber operates as electrical insulation. In this study, SDDM specimens were fabricated, and tensile and impact tests were performed. The tensile tests of SDDM specimens find two distinct loading peaks: first where the carbon fiber fails, and second where the glass fiber fails. A linear correlation was observed between the carbon fiber resistance and composite strain up to a threshold, beyond which a sharp nonlinear increase in resistance occurred. The resistance then approached infinity, coinciding with the first loading peak and failure of the carbon fiber elements. This demonstrates the potential for a damage early warning threshold. Additionally, the effect of stitching the sensor tow in a zig-zag pattern over a large area was investigated using tailored fiber placement (TFP) of 1-loop, 3-loop, and 5-loop specimens. Tensile testing found that increasing the number of loops improved the sensor’s accuracy for strain sensing. Furthermore, impact tests were conducted, and as the impact energy progressively increased, the sensor resistance permanently increased. This illustrates a capability for self-memory of microdamage throughout the life cycle of the structure, potentially useful for predicting the remaining life of the composite.

Demo, Luke B. (ORCID:0000000208806522)↗

HAMR - Heterogeneous Accelerator Memory Resource (HAMR) v1.0

HAMR is a library defining an accelerator technology agnostic memory model that bridges between accelerator technologies (CUDA, HIP, ROCm, OpenMP, Sycl, OpenCL, Kokos, etc) and traditional CPUs in heterogeneous computing environments. HAMR is light weight and implemented in modern C++. HAMR can be used to manage memory with in a single code or as a data model for coupling codes in a technologically agnostic way. HAMR provides a Python module for coupling C++ and Python codes which implements zero-copy data transfers to and from Python using the Numpy array interface and Numba CUDA array interface protocols.

Loring, Burlen↗