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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 883 records · Page 49
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NASA NTRS2005

MSAP Hardware Verification: Testing Multi-Mission System Architecture Platform Hardware Using Simulation and Bench Test Equipment

The Multi-Mission System Architecture Platform (MSAP) project aims to develop a system of hardware and software that will provide the core functionality necessary in many JPL missions and can be tailored to accommodate mission-specific requirements. The MSAP flight hardware is being developed in the Verilog hardware description language, allowing developers to simulate their design before releasing it to a field programmable gate array (FPGA). FPGAs can be updated in a matter of minutes, drastically reducing the time and expense required to produce traditional application-specific integrated circuits. Bench test equipment connected to the FPGAs can then probe and run Tcl scripts on the hardware. The Verilog and Tcl code can be reused or modified with each design. These steps are effective in confirming that the design operates according specifications.

Crossin, Kent R.↗
NASA NTRS2001

Considerations on communications network protocols in deep space

Communications supporting deep space missions impose numerous unique constraints that impact the architectural choices made for cost-effectiveness. We are entering the era where networks that exist in deep space are needed to support planetary exploration. Cost-effective performance will require a balanced integration of applicable widely used standard protocols with new and innovative designs.

network protocols deep space wireless networks↗
NASA NTRS2006

Power Actuation and Switching Module Test Results

The X2000 Power System Electronics (PSE) is a Jet Propulsion Laboratory (JPL) task to develop a new generation of power system building blocks for use on future deep-space missions. The effort includes the development of electronic components and modules that can be used as building blocks in the design of generic spacecraft power systems. All X2000 avionics components and modules are designed for use in centralized or distributed spacecraft architectures. The Power Actuation and Switching Module (PASM) has been developed under the X2000 program. This component enables a modular and scalable design approach for power switching applications, which can result in a wide variety of power switching architectures using this simple building block. The PASM is designed to provide most of the necessary power switching functions of spacecraft for various Deep Space missions including future missions to Mars, comets, Jupiter and its moons. It is fabricated using an ASIC process that is tolerant of high radiation. The development included two application specific integrated circuits (ASICs) and support circuitry all packaged using High Density Interconnect (HDI) technology. It can be operated in series or parallel with other PASMs. It can be used as a high-side or low-side switch and it can drive thruster valves, pyrotechnic devices such as NASA standard initiators, bus shunt resistors, and regular spacecraft component loads. Each PASM contains two independent switches with internal current limiting and over-current trip-off functions to protect the power subsystem from load faults. During turnon and turnoff each switch can limit the rate of current change (di/dt) to a value determined by the user. Three-way majority-voted On/Off commandability and full switch status telemetry (both analog and digital) are built into the module. This paper is a follow up to the one presented at he IECEC 2004 conference that will include the lessons learned and test results from the development.

X2000↗
NASA NTRS2006

BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

Berger, Richard↗
NASA NTRS2000

Intelligent subsystem interface for modular hardware system

A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.

Krening, Douglas N.↗
NASA NTRS2008

Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Reinhart, Richard C.↗
NASA NTRS2008

Hardware Architecture Study for NASA's Space Software Defined Radios

This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Reinhart, Richard C.↗
NASA NTRS2008

MEMS Microshutter Array System for James Webb Space Telescope

A complex MEMS microshutter array system has been developed at NASA Goddard Space Flight Center (GSFC) for use as a multi-object aperture array for a Near-Infrared Spectrometer (NIRSpec). The NIRSpec is one of the four major instruments carried by the James Webb Space Telescope (JWST), the next generation of space telescope after the Hubble Space Telescope retires. The microshutter arrays (MSAs) are designed for the selective transmission of light with high efficiency and high contrast. It is demonstrated in Figure 1 how a MSA is used as a multiple object selector in deep space. The MSAs empower the NIRSpec instrument simultaneously collect spectra from more than 100 targets therefore increases the instrument efficiency 100 times or more. The MSA assembly is one of three major innovations on JWST and the first major MEMS devices serving observation missions in space. The MSA system developed at NASA GSFC is assembled with four quadrant fully addressable 365x171 shutter arrays that are actuated magnetically, latched and addressed electrostatically. As shown in Figure 2, each MSA is fabricated out of a 4' silicon-on-insulator (SOI) wafer using MEMS bulk-micromachining technology. Individual shutters are close-packed silicon nitride membranes with a pixel size close to 100x200 pm (Figure 3). Shutters are patterned with a torsion flexure permitting shutters to open 90 degrees with a minimized mechanical stress concentration. In order to prevent light leak, light shields are made on to the surrounding frame of each shutter to cover the gaps between the shutters and the Game (Figure 4). Micro-ribs and sub-micron bumps are tailored on hack walls and light shields, respectively, to prevent sticktion, shown in Figures 4 and 5. JWST instruments are required to operate at cryogenic temperatures as low as 35K, though they are to be subjected to various levels of ground tests at room temperature. The shutters should therefore maintain nearly flat in the entire temperature range between 35K and 300K. Through intensive numerical simulations and experimental studies, an optically opaque and electrically conductive metal-nitride thin film was selected as a coating material deposited on the shutters with the best thermal-expansion match to silicon nitride - the shutter blade thin film material. A shutter image shown in Figure 6 was taken at room temperature, presenting shutters slightly bowing down as expected. Shutters become flat when the temperature decreases to 35K. The MSAs are then bonded to silicon substrates that are fabricated out of 6" single-silicon wafers in the thickness of 2mm. The bonding is conducted using a novel single-sided indium flip-chip bonding technology. Indium bumps fabricated on a substrate are shown in Figure 7. There are 180,000 indium bumps for bonding a flight format MSA array to its substrate. Besides a MSA, each substrate houses five customer-designed ASIC (Application Specific Integrated Circuit) multiplexer/address chips for 2-dimensional addressing, twenty capacitors, two temperature sensors, numbers of resistors and all necessary interconnects, as shown in Figure 8. Complete MSA quadrant assemblies have been successfully manufactured and fully functionally tested. The assemblies have passed a series of critical reviews required by JWST in satisfying all the design specifications. The qualification tests cover programmable 2-D addressing, life tests, optical contrast tests, and environmental tests including radiation, vibration, and acoustic tests. A 2-D addressing pattern with 'ESA' letters programmed in a MSA is shown in Figure 9. The MSAs passed 1 million cycle life tests and achieved high optical contrast over 10,000. MSA teams are now making progress in final fabrication, testing and assembly (Figure 10). The delivery of flight-format MSA system is scheduled at the end of 2008 for being integrated to the focal plane of the NIRSpec detectors.

Li, Mary J.↗
NASA NTRS2007

Detector Arrays for the James Webb Space Telescope Near-Infrared Spectrograph

The James Webb Space Telescope's (JWST) Near Infrared Spectrograph (NIRSpec) incorporates two 5 micron cutoff (lambda(sub co) = 5 microns) 2048x2048 pixel Teledyne HgCdTe HAWAII-2RG sensor chip assemblies. These detector arrays, and the two Teledyne SIDECAR application specific integrated circuits that control them, are operated in space at T approx. 37 K. In this article, we provide a brief introduction to NIRSpec, its detector subsystem (DS), detector readout in the space radiation environment, and present a snapshot of the developmental status of the NIRSpec DS as integration and testing of the engineering test unit begins.

Rauscher, Bernard J.↗
NASA NTRS2008

James Webb Space Telescope Near-Infrared Spectrograph: Dark Performance of the First Flight Candidate Detector Arrays

The James Webb Space Telescope (JWST) Near Infrared Spectrograph (NIRSpec) incorporates two 5 micron cutoff (lambda(sub co) = 5 micron) 2048x2048 pixel Teledyne HgCdTe HAWAII-2RG sensor chip assemblies. These detector arrays, and the two Teledyne SIDECAR application specific integrated circuits that control them, are operated in space at T approx. 37 K. This article focuses on the measured performance of the first flight-candidate, and near-flight candidate, detector arrays. These are the first flight-packaged detector arrays that meet NIRSpec's challenging 6 e(-) rms total noise requirement.

Rauscher, Bernard J.↗
NASA NTRS2008

Replication of Space-Shuttle Computers in FPGAs and ASICs

A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

Ferguson, Roscoe C.↗
NASA NTRS2008

Fault-Tolerant Coding for State Machines

Two reliable fault-tolerant coding schemes have been proposed for state machines that are used in field-programmable gate arrays and application-specific integrated circuits to implement sequential logic functions. The schemes apply to strings of bits in state registers, which are typically implemented in practice as assemblies of flip-flop circuits. If a single-event upset (SEU, a radiation-induced change in the bit in one flip-flop) occurs in a state register, the state machine that contains the register could go into an erroneous state or could hang, by which is meant that the machine could remain in undefined states indefinitely. The proposed fault-tolerant coding schemes are intended to prevent the state machine from going into an erroneous or hang state when an SEU occurs. To ensure reliability of the state machine, the coding scheme for bits in the state register must satisfy the following criteria: 1. All possible states are defined. 2. An SEU brings the state machine to a known state. 3. There is no possibility of a hang state. 4. No false state is entered. 5. An SEU exerts no effect on the state machine. Fault-tolerant coding schemes that have been commonly used include binary encoding and "one-hot" encoding. Binary encoding is the simplest state machine encoding and satisfies criteria 1 through 3 if all possible states are defined. Binary encoding is a binary count of the state machine number in sequence; the table represents an eight-state example. In one-hot encoding, N bits are used to represent N states: All except one of the bits in a string are 0, and the position of the 1 in the string represents the state. With proper circuit design, one-hot encoding can satisfy criteria 1 through 4. Unfortunately, the requirement to use N bits to represent N states makes one-hot coding inefficient.

Naegle, Stephanie Taft↗
NASA NTRS2007

Advanced High-Definition Video Cameras

A product line of high-definition color video cameras, now under development, offers a superior combination of desirable characteristics, including high frame rates, high resolutions, low power consumption, and compactness. Several of the cameras feature a 3,840 2,160-pixel format with progressive scanning at 30 frames per second. The power consumption of one of these cameras is about 25 W. The size of the camera, excluding the lens assembly, is 2 by 5 by 7 in. (about 5.1 by 12.7 by 17.8 cm). The aforementioned desirable characteristics are attained at relatively low cost, largely by utilizing digital processing in advanced field-programmable gate arrays (FPGAs) to perform all of the many functions (for example, color balance and contrast adjustments) of a professional color video camera. The processing is programmed in VHDL so that application-specific integrated circuits (ASICs) can be fabricated directly from the program. ["VHDL" signifies VHSIC Hardware Description Language C, a computing language used by the United States Department of Defense for describing, designing, and simulating very-high-speed integrated circuits (VHSICs).] The image-sensor and FPGA clock frequencies in these cameras have generally been much higher than those used in video cameras designed and manufactured elsewhere. Frequently, the outputs of these cameras are converted to other video-camera formats by use of pre- and post-filters.

Glenn, William↗
NASA NTRS2007

Improved On-Chip Measurement of Delay in an FPGA or ASIC

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Chen, Yuan↗
NASA NTRS2010

Radiation-Hardened Solid-State Drive

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

Sheldon, Douglas J.↗
NASA NTRS2010

Reconfigurable Hardware for Compressing Hyperspectral Image Data

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of the FPGAs makes it possible to effectively alter the design to some extent to satisfy different requirements without adding hardware. The implementation could be easily propagated to future FPGA generations and/or to custom application-specific integrated circuits.

Aranki, Nazeeh↗
NASA NTRS2009

Optimization of digital designs

An application specific integrated circuit is optimized by translating a first representation of its digital design to a second representation. The second representation includes multiple syntactic expressions that admit a representation of a higher-order function of base Boolean values. The syntactic expressions are manipulated to form a third representation of the digital design.

Whitaker, Sterling R.↗